Prosecution Insights
Last updated: October 27, 2026
Application No. 18/613,655

NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT

Final Rejection §102§103
Filed
Mar 22, 2024
Priority
Mar 22, 2023 — JP 2023-045022
Examiner
KEBEDE, BROOK
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Nikkiso Co., Ltd.
OA Round
2 (Final)
89%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
926 granted / 1042 resolved
+20.9% vs TC avg
Minimal +4% lift
Without
With
+4.5%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
25 currently pending
Career history
1059
Total Applications
across all art units

Statute-Specific Performance

§101
2.2%
-37.8% vs TC avg
§103
35.9%
-4.1% vs TC avg
§102
30.3%
-9.7% vs TC avg
§112
12.3%
-27.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1042 resolved cases

Office Action

§102 §103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over MATSUKURA et al. (US 2021/0043802). PNG media_image1.png 627 591 media_image1.png Greyscale Re Claim 1, MATSUKURA et al. disclose a nitride semiconductor light-emitting element, comprising: an n-type semiconductor layer (30, i.e., n-type cladding layer) comprising Al, Ga and N (Fig. 1, Paragraph [0034]); an active layer (50, Paragraph [0026]) that is formed on one side of the n-type semiconductor layer (30, Fig. 1) and comprises a well layer (54, Paragraphs [0037]-[0038]) comprising Al, Ga and N (Paragraph [0039]) and a barrier layer (52, Paragraph [0038]) comprising Al, Ga and N (Paragraph [0039]) and having a higher Al composition ratio than that of the well layer (see Fig. 2 and Paragraph [0039]); an electron blocking layer (60) that is formed on the active layer (50) on an opposite side to the n-type semiconductor layer (30) and comprises Al and N (Paragraph [0042]); and a p-type semiconductor layer (80, i.e., p-type contact layer, Paragraph [0042]) formed on the electron blocking layer on an opposite side to the active layer (see Fig. 1), wherein the electron blocking layer (60) comprises a plurality of semiconductor layers that are undoped (i.e., first electron blocking layer 61, Paragraph [0043]), wherein among the plurality of semiconductor layers constituting the electron blocking layer, a first electron blocking layer (61) located closest to the active layer (50) has a higher Al composition ratio than that of the other semiconductor layers constituting the electron blocking layer and that of the barrier layer (see Fig. 2), and wherein a film thickness of the first electron blocking layer (61) is less than 4 nm; and the p-type semiconductor layer has a predetermined thickness (Paragraph [0049], i.e., between 1 nm and 10 nm, that encompassed claimed range of less 2 nm). See Figs. 1-2 and related text in Paragraphs [0029] – [0061]. Furthermore, the claimed thickness of the p-typed semiconductor layer neither novel nor nonobvious and can produced by routine optimization and the range is within the scope of MATSUKURA et al. disclosure. Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Re Claims 3 and 4, as applied to claim 1 above, MATSUKURA et al. disclose all the claimed limitations including wherein the p-type semiconductor layer (80) comprises a p-type contact layer comprising p-type GaN (Paragraph [0052]). Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over MATSUKURA et al. (US 2021/0043802) in view of MATSUKURA et al. (US 2022/0131042). Re Claim 5, as applied to claim 1 above, MATSUKURA et al. disclose all the claimed limitations. However, MATSUKURA et al. ’0043802 do not disclose silicon is included at an interface between the electron blocking layer and the p-type semiconductor layer. MATSUKURA et al. ’0131042 disclose silicon is included at an interface between the electron blocking layer and the p-type semiconductor layer (i.e., the electron blocking layer is doped with silicon (Si) as an n-type impurity a p-type impurity from the p-type semiconductor layer is attracted to the silicon in the electron blocking layer and diffusion of the p-type impurity into the active layer is suppressed, hence, life of the nitride semiconductor light-emitting element is extended) see Paragraph [0004]. Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to provide MATSUKURA et al. ’0043802 reference with silicon is included at an interface between the electron blocking layer and the p-type semiconductor layer as taught by MATSUKURA et al. ’0131042 in order to suppress diffusion of the p-type impurity into the active layer and thereby to enhance the shell-life of the nitride semiconductor light-emitting element. Response to Arguments Applicant's arguments filed July 20, 20256 have been fully considered but they are not persuasive. Applicant’s argument with respect to thickness of the p-type semiconductor layer has no merit because such thickness is within scope of MATSUKURA et al. disclosure. Therefore, the rejection of claim 1 under 35 U.S.C. 102 is deemed proper. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Correspondence Any inquiry concerning this communication or earlier communications from the examiner should be directed to BROOK KEBEDE whose telephone number is 571-272-1862. The examiner can normally be reached Monday Friday 8:00 AM 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BROOK KEBEDE/ Primary Examiner, Art Unit 2894 /BK/ April 30, 2026
Read full office action

Prosecution Timeline

Mar 22, 2024
Application Filed
May 08, 2026
Non-Final Rejection mailed — §102, §103
Jul 20, 2026
Response Filed
Oct 02, 2026
Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
89%
Grant Probability
93%
With Interview (+4.5%)
2y 1m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1042 resolved cases by this examiner. Grant probability derived from career allowance rate.

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