Prosecution Insights
Last updated: April 19, 2026
Application No. 18/613,761

DRIVING DEVICE AND POWER CONVERTER

Non-Final OA §103
Filed
Mar 22, 2024
Examiner
CHOI, SEUNG HO
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fuji Electric Co. Ltd.
OA Round
1 (Non-Final)
100%
Grant Probability
Favorable
1-2
OA Rounds
2y 7m
To Grant
0%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allow Rate
1 granted / 1 resolved
+32.0% vs TC avg
Minimal -100% lift
Without
With
+-100.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
12 currently pending
Career history
13
Total Applications
across all art units

Statute-Specific Performance

§103
100.0%
+60.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1 resolved cases

Office Action

§103
DETAILED ACTION This Office action is in response to the application filed on 22 March 2024. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Specification The disclosures are objected to because of the following informalities: In the paragraph 0029, “Accordingly, during the mode MD2” should change to “Accordingly, during the mode MD3”. Drawings objection PNG media_image1.png 431 578 media_image1.png Greyscale Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 7, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Igarashi Hisakatsu et. al (JP-2017051049A, 2017; hereafter “Hisakatsu”) in the view of Tsuyoshi Funaki et. al (2013 4th IEEE International Symposium on Power Electronics for Distributed Generation Systems (PEDG), DOI: 10.1109/PEDG.2013.6785593 ; hereafter “Funaki”). -regarding Claim 1: Hisakatsu discloses; PNG media_image2.png 514 880 media_image2.png Greyscale A driving device (Fig. 2; 1a and 1b) configured to alternately switch a first switching element (Fig. 2; 2a) and a second switching element (Fig. 2; 2b) that are coupled in series, with a dead time (Fig. 3; MD2, MD4) in between and during which the first switching element and the second switching element are simultaneously turned off, the driving device comprising: a first drive circuit (Fig. 1; 1a,GDU, Hisakatsu discloses three pairs of switching elements with 6 GDUs (1a-1f), and the inventor discloses only one pair of switching elements) configured to drive the first switching element; and a second drive circuit (Fig. 1; 1b, GDU) configured to drive the second switching element, wherein the first drive circuit includes: a first control line (Fig. 5; blue arrow) electrically connected to a control electrode of the first switching element, a first positive power supply line (Fig. 5; red arrow) set to a first positive power supply voltage (Fig. 5; P1), a first negative power supply line (Fig. 5; yellow arrow) set to a first negative power supply voltage (Fig. 5; N1first switching circuit (Fig. 5; switch 106) configured to switch between electrically connecting and not electrically connecting the first control line to the first positive power supply line, a second switching circuit (Fig. 5; switch 107) configured to switch between electrically connecting or not electrically connecting the first control line to the first negative power supply line, first control circuit (Fig. 5; 108, which taught how to control the connection between intermediate voltage and SiC MOSFET during the dead time)the second drive circuit (Fig. 1; 1b, GDU) includes: a second control line(Fig. 5; blue arrow) electrically connected to a control electrode of the second switching element, a second positive power supply line (Fig. 5; red arrow) set to a second positive power supply voltage(Fig. 5; P1), a second negative power supply line(Fig. 5; yellow arrow) set to a second negative power supply voltage(Fig. 5; N1), a fourth switching circuit (Fig. 5; switch 106) configured to switch between electrically connecting and not electrically connecting the second control line to the second positive power supply line, a fifth switching circuit (Fig. 5; switch 107) configured to switch between electrically connecting and not electrically connecting the second control line to the second negative power supply line, second control circuit (Fig. 5; 108, which taught how to control the connection between intermediate voltage and SiC MOSFET during the dead time) However, Hisakatsu does not disclose the third and the sixth switching circuits for applying a mid-voltage to the switching elements during the dead time. PNG media_image3.png 270 542 media_image3.png Greyscale PNG media_image4.png 406 672 media_image4.png Greyscale Funaki discloses; a first reference line electrically connected to a first main electrode of the first switching element, and set to a first intermediate voltage (above Fig. 1; power supply) higher than the first negative power supply voltage and lower than a threshold voltage of the first switching element, a third switching circuit configured to switch between electrically connecting and not electrically connecting the first control line to the first reference line, and a first control circuit configured to operate the third switching circuit so that the first control line is electrically connected to the first reference line during the dead time (above Fig. 2; the part of third switching circuit in claim 1 is based on characteristic graph of SiC MOSFET). a second reference line electrically connected to a first main electrode of the second switching element, and set to a second intermediate voltage (above Fig. 1; power supply) higher than the second negative power supply voltage and lower than a threshold voltage of the second switching element, a sixth switching circuit configured to switch between electrically connecting and not electrically connecting the second control line to the second reference line, and a second control circuit configured to operate the sixth switching circuit so that the second control line is electrically connected to the second reference line (above Fig. 2; the part of sixth switching circuit in claim 1 is based on characteristic graph of SiC MOSFET). Funaki discloses the characteristic change of Sic MOSFET during its operation in his paper. His paper focuses on the operation of body diode in SiC MOSFET, and studies the performance degradation in conduction and blocking capability of SiC MOSFET for the long duration dc current conduction of body diode and freewheeling current conduction of body diode in switching operation of MOSFET. Funaki taught and gave a motivation to apply intermediate voltage to the body diode of SiC MOSFET through the third switching circuit during the dead time to decrease the current between drain and source. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Hisakatsu such that the characteristic graph of SiC MOSFET as studied in Funaki taught and gave a motivation to the third switching circuit for applying the intermediate voltage into the switching element. Doing so allows for preventing deterioration of the switching element during the dead time. -regarding Claim 7: Hisakatsu discloses; A power converter (Fig. 1) comprising: the driving device according to claim 1; the first switching element (Fig. 2; 2a); and the second switching element (Fig. 2; 2b). -regarding Claim 9: Hisakatsu discloses; The power converter as claimed in claim 7, wherein the first switching element and the second switching element are elements formed of a wide bandgap semiconductor (Fig. 5; 3b). Allowable Subject Matter Claims 2-6,8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim. The following is a statement of reasons for the indication of allowable subject matter: -with respect to claim 2: the prior arts in Hisakatsu and Funaki disclose the claimed invention in basic claims but do not further disclose resistive elements coupled in series to the switching circuit between the control line and the reference line, -with respect to claim 3: the prior arts in Hisakatsu and Funaki disclose the claimed invention in basic claims but do not further disclose resistive elements coupled in series to the switching circuit between the control line and the positive power supply line -with respect to claim 6: the prior arts in Hisakatsu and Funaki disclose the claimed invention in basic claims but do not further disclose about the bidirectional switching circuits. -with respect to claim 8: the prior arts in Hisakatsu and Funaki disclose the claimed invention in basic claim but do not further disclose a seventh resistive element and an eighth resistive element coupled to or inserted in series in the control line. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The reference (Xuning Zhang, Figure 4) discloses that the intermediate voltage applies to a body diode of SiC MOSFET. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEUNG HO CHOI whose telephone number is (571)272-8188. The examiner can normally be reached Monday-Thursday, 7:30 AM - 5:30 PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached at 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SEUNG HO CHOI/Examiner, Art Unit 2838 /CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838
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Prosecution Timeline

Mar 22, 2024
Application Filed
Jan 30, 2026
Non-Final Rejection — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
100%
Grant Probability
0%
With Interview (-100.0%)
2y 7m
Median Time to Grant
Low
PTA Risk
Based on 1 resolved cases by this examiner. Grant probability derived from career allow rate.

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