CTNF 18/613,829 CTNF 101872 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-25 AIA Applicant's election with traverse of claims 1-11 in the reply filed on May 18, 2026 is acknowledged. The traversal is on the ground(s) that there is no This is not found persuasive because undue burden is not based on the amount of claims, rather based on the subject of the claims in light of the identified groups. Each group would require different search strategies and queries . The requirement is still deemed proper and is therefore made FINAL. 08-05 AIA Claim s 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention , there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on May 18, 2026 . Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. 23-19 AIA Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application. Information Disclosure Statement The information disclosure statements (IDS) submitted on November 7, 2024 and April 29, 2025 are in compliance with time for filing requirements of 3 7 C.F.R. 1.97, and thus, the information disclosure statement has been considered except as otherwise indicated. Drawings 06-22-07 AIA The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: Fig. 6: element 520 Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. 06-11-01 AIA The following title is suggested: Internal Gate Dielectric and . Claim Objections 07-29-01 AIA Claim s 4 and objected to because of the following informalities: Claim 4: Claim 10: The language used in the limitation “a direction in which the first source electrode and the first drain electrode are spaced apart from each other” should read as “in the second direction” . Appropriate correction is required. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-7 and 9 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Gardner et al. (US20230114024A1) . Regarding Claim 1: Gardner discloses a semiconductor device (3D transistor structure; Fig. 1B) comprising: a first channel layer (First 2D channel; Fig. 1B element 250A) and a second channel layer (Second 2D channel; Fig. 1B element 250A) spaced apart from each other in a first direction (downward), the first channel layer including a first two-dimensional (2D) semiconductor material and the second channel layer including a second 2D semiconductor material, the second 2D semiconductor material the same as or different from the first 2D semiconductor material (Fig. 1B elements 110 and 111, paragraphs 38-41); a first source electrode (Fig. 1B element 215A) between the first channel layer (element 250A) and the second channel layer (element 250A) to be simultaneously in contact with the first channel layer and the second channel layer (paragraph 72); a first drain electrode (Fig. 1B element 220A) between the first channel layer (element 250A) and the second channel layer (element 250A) to be spaced apart from the first source electrode (element 215A) in a second direction (x axis; Fig. 19) that is perpendicular to the first direction and to be simultaneously in contact with the first channel layer and the second channel layer (paragraph 72); a first gate electrode (Fig. 1B element 145) in a first internal space (Fig. 1B) surrounded by the first source electrode (element 215A), the first drain electrode (element 220A), the first channel layer (First 2D channel), and the second channel layer (Second 2D channel); and a first gate insulating layer (Fig. 1B elements 140 and 125) surrounding (see Fig. 19) the first gate electrode (element 145) in the first internal space. Regarding Claim 2: Gardner discloses a semiconductor device (3D transistor structure; Fig. 1B) according to claim 1, further comprising: a lower gate electrode (lower 235A; Fig. 1B element 145); and a lower insulating layer (lower High K Gate; Fig. 1B element 140) between the lower gate electrode and the first channel layer (element 250). Regarding Claim 3: Gardner discloses a semiconductor device (3D transistor structure; Fig. 1B) according to claim 1, further comprising: an upper gate electrode (upper 235B; Fig. 1B element 146); and an upper insulating layer (upper High K Gate; Fig. 1B element 140) between the upper gate electrode and the second channel layer (element 250). Regarding Claim 4: Gardner discloses a semiconductor device (3D transistor structure; Fig. 1B) according to claim 1, further comprising: a third channel layer (Fig. 1B element 250B) spaced apart from the second channel layer (element 250A) in the first direction (downward) and including a third 2D semiconductor material (element 111), the third 2D semiconductor material same as or different from the first 2D semiconductor material and same as or different from the first 2D semiconductor material (Fig. 1B elements 110 and 111, paragraphs 38-41). Regarding Claim 5: Gardner discloses a semiconductor device (3D transistor structure; Fig. 1B) according to claim 4, further comprising: a second source electrode (Fig. 1B element 215B) between the second channel layer and the third channel layer (elements 250, 110, and 111) to be simultaneously in contact with the second channel layer and the third channel layer (paragraph 72); a second drain electrode (Fig. 1B element 220B) between the second channel layer and the third channel layer (elements 250) to be spaced apart from the second source electrode (element 215B) in a second direction (x axis; Fig. 19) that is perpendicular to the first direction (downward) and to be simultaneously in contact with the second channel layer and the third channel layer (paragraph 72); a second gate electrode (lower 235B; Fig. 1B element 146) in a second internal space surrounded by the second source electrode (element 215B), the second drain electrode (element 220B), the second channel layer (elements 250, 110, and 111), and the third channel layer (elements 250, 110, and 111); and a second gate insulating layer (Fig. 1B elements 140 and 125) surrounding (see Fig. 1B) the second gate electrode (element 146) in the second internal space. Regarding Claim 6: Gardner discloses a semiconductor device (3D transistor structure; Fig. 1B) according to claim 1, wherein the first 2D semiconductor material includes one or more of MoS- 2 , MoSe 2 , MoTe 2 , WS 2 , WSe 2 , MoTe 2 , or PtSe 2 , and the second 2D semiconductor material includes one or more of MoS 2 , MoSe 2 , MoTe 2 , WS 2 , WSe 2 , MoTe 2 , or PtSe 2 (paragraph 30). Regarding Claim 7: Gardner discloses a semiconductor device (3D transistor structure; Fig. 1B) according to claim 1, wherein either or both the first 2D semiconductor material and the second 2D semiconductor material includes a metal element selected from among Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge, and Pb and a chalcogen element selected from among S, Se, and Te (paragraph 30). Regarding Claim 9: Gardner discloses a semiconductor device (3D transistor structure; Fig. 1B) according to claim 1, wherein the first channel layer and the second channel layer each independently have a thickness of 3 nm or less (paragraph 30) . 07-15 AIA Claim 11 is rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by O'Brien et al. (US20230101760A1) . Regarding Claim 11: O’Brien discloses an electronic apparatus (computing device; Fig. 4) comprising: a semiconductor device (Fig. 2 element 201); and a controller configured to control the semiconductor device (Fig. 4 elements 400 and 402, paragraphs 56-60), wherein the semiconductor device comprises: a first channel layer and a second channel layer (Fig. 2 elements 211) that are arranged to be spaced apart from each other in a first direction (Fig. 2, paragraphs 69-81), the first channel layer including a first two-dimensional (2D) semiconductor material, the second channel layer including a second 2D semiconductor material that is same as or different from the first 2D semiconductor material layer (paragraphs 26, 32, and 42); a first source electrode (Fig. 2 elements 215/214, paragraph 38) between the first channel layer (element 211) and the second channel layer (element 211) to be simultaneously in contact with the first channel layer and the second channel layer (paragraphs 35 and 38); a first drain electrode (Fig. 2 elements 215/214, paragraph 38) between the first channel layer (element 211) and the second channel layer (element 211) to be spaced apart from the first source electrode in a second direction perpendicular to the first direction (Fig. 2, paragraph 26) and simultaneously in contact with the first channel layer and the second channel layer (paragraphs 35 and 38); a first gate electrode (Fig. 2 element 212) arranged in a first internal space (Fig. 3G, paragraphs 48 and 54) surrounded by the first source electrode (elements 215/214), the first drain electrode (elements 215/214), the first channel layer (elements 211), and the second channel layer (elements 211); and a first gate insulating layer (Fig. 2 element 213, paragraph 33) arranged to surround the first gate electrode (Fig. 2 element 212) in the first internal space (Fig. 3G, paragraph 54) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-02-aia AIA Claim s 8 and 10 are rejected under 35 U.S.C. 103 as being obvious over Gardner et al. (US20230114024A1) in view of Seol et al. (US20220077321A1) . The applied reference has a common assignee and joint inventor with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This reference also qualifies as prior art under 35 U.S.C. 102(a)(1). Regarding Claim 8: Gardner discloses a semiconductor device (3D transistor structure; Fig. 1B) according to claim 1 with a first channel layer (First 2D channel; Fig. 1B element 250A) and a second channel layer (Second 2D channel; Fig. 1B element 250A), each including a respective 2D semiconductor material. However, Gardner does not explicitly teach where the first and second channel layers each independently include a double or triple-layered structure. Seol discloses an analogous field effect transistor (Fig. 2 element 100) with a first channel layer (element 141) and a second layer (element 142), wherein the first channel layer and the second channel layer each independently include a double or triple-layered structure including the respective first 2D semiconductor material or the second 2D semiconductor material (paragraphs 65 and 81). It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the device described in Gardner further in view of Seol such that the first and second channel layers each independently include a double or triple-layered structure because both are directed to analogous semiconductor devices. Doing so allows for a lower channel length and further minimization of semiconductor devices (Seol, paragraphs 5 and 82). Regarding Claim 10: Gardner discloses a semiconductor device (3D transistor structure; Fig. 1B) according to claim 1 with a first gate electrode (Fig. 1B element 145) between a first source electrode (Fig. 1B element 215A) and a first drain electrode (Fig. 1B element 220A). However, Gardner does not explicitly teach a length of the first gate in a second direction to be 10 nm or less. Seol discloses an analogous field effect transistor (Fig. 2 element 100) with a first gate electrode (element 160), wherein a length CL of said gate electrode in a direction (x-direction) in which the first source electrode (element 120) and the first drain electrode (element 130) are spaced apart from each other is 10 nm or less (paragraph 67). It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the device described in Gardner further in view of Seol such that the length of the first gate electrode is 10 nm or less in a second direction because both are directed to analogous semiconductor devices. Doing so allows for a lower channel length and further minimization of the semiconductor device (Seol, paragraphs 3-5) . This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02. Citation of Pertinent Prior Art 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Naylor et alLee et al. (US 20240113191 A1), Kim et al. (US 20230387279 A1), Lee et al. (US 20210296445 A1) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Chloë E Benton whose telephone number is (571)272-9976. The examiner can normally be reached Monday-Thursday: 8am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Chloë E Benton/Examiner, Art Unit 2899 /ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899 Application/Control Number: 18/613,829 Page 2 Art Unit: 2899 Application/Control Number: 18/613,829 Page 3 Art Unit: 2899 Application/Control Number: 18/613,829 Page 4 Art Unit: 2899 Application/Control Number: 18/613,829 Page 5 Art Unit: 2899 Application/Control Number: 18/613,829 Page 6 Art Unit: 2899 Application/Control Number: 18/613,829 Page 7 Art Unit: 2899 Application/Control Number: 18/613,829 Page 8 Art Unit: 2899 Application/Control Number: 18/613,829 Page 9 Art Unit: 2899 Application/Control Number: 18/613,829 Page 10 Art Unit: 2899
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