Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 18, the phrase "or the like" renders the claim(s) indefinite because the claim(s) include(s) elements not actually disclosed (those encompassed by "or the like"), thereby rendering the scope of the claim(s) unascertainable. See MPEP § 2173.05(d).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 10355004 B2) in view of Yamazaki et al. (US 20220130844 A1).
Regarding claim 1, Choi et al. disclose a one-time programmable (OTP) memory device comprising:
a semiconductor substrate (SUB, Fig. 2) having a write region and a read region (regions of WR and RG, Fig. 2, paragraph 6);
write gates disposed in the write region of the semiconductor substrate (WG on write region, Fig. 2, paragraph 6);
read gates disposed in the read region of the semiconductor substrate (RG on read region, Fig. 2, paragraph 6);
a device isolation layer (ISO, Fig. 1) located between the write gates and arranged in the semiconductor substrate (Fig. 1),
wherein a pocket well (impurity well 99, Fig. 2) is formed in the write region (formed in the write region of WG, Fig. 2) of the semiconductor substrate and has the second conductivity type (n-type, paragraph 42).
However, Choi et al. do not disclose the source/drain regions arranged adjacent to the write gates and the read gates and arranged in the semiconductor substrate; wherein, in the semiconductor substrate, channel regions located below the write gates have a first conductivity type, wherein the source/drain regions have a second conductivity type, different from the first conductivity type.
However, Yamazaki et al. disclose the source/drain regions (source region 14 and drain region 13, Fig. 2) arranged adjacent to the write gates and the read gates (gate 16) and arranged in the semiconductor substrate (11, Fig. 2);
wherein, in the semiconductor substrate, channel regions (12) located below the write gates have a first conductivity type (channel region is integrated to substrate 11, which is p-type, paragraph 22),
wherein the source/drain regions (source 14 and drain 13, Fig. 2) have a second conductivity type (n-type, paragraph 27), different from the first conductivity type.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Choi et al. in view of Yamazaki et al. such that the source/drain regions arranged adjacent to the write gates and the read gates and arranged in the semiconductor substrate; wherein, in the semiconductor substrate, channel regions located below the write gates have a first conductivity type, wherein the source/drain regions have a second conductivity type, different from the first conductivity type. Doing so would enable efficient, high-density, and low-power memory operation.
Regarding claim 4, Choi et al. discloses the semiconductor substrate has the first conductivity type (p-type, paragraph 60), the first conductivity type is p-type, and the second conductivity type is n-type.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 10355004 B2) in view of Yamazaki et al. (US 20220130844 A1) as applied to claim 1 above, in further view of Chen et al. (US 10090309 B1).
Regarding claim 2, Choi and Yamazaki are discussed above. Choi discloses a second sidewall of the pocket well (99) is in contact with the semiconductor substrate (SUB).
Neither Choi nor Yamazaki disclose a vertical level of a bottom surface of the device isolation layer is lower than a vertical level of a bottom surface of the pocket well, wherein a first sidewall of the pocket well is in contact with the device isolation layer
However, Chen et al. disclose a vertical level of a bottom surface of the device isolation layer (120) is lower than a vertical level of a bottom surface of the pocket well (132, Fig. 2), wherein a first sidewall of the pocket well (132) is in contact with the device isolation layer (120, Fig. 2)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Choi and Yamazaki in view of Chen et al. such that the vertical level of a bottom surface of the device isolation layer is lower than a vertical level of a bottom surface of the pocket well, wherein a first sidewall of the pocket well is in contact with the device isolation layer. Doing so would prevent electrical crosstalk and restrict leakage between adjacent memory cells.
Regarding claim 3, Choi and Yamazaki are discussed above. Neither reference discloses the pocket well is located to contact the channel regions of the write gates and the source/drain regions of the write gates.
However, Chen discloses the pocket well (132) is located to contact the channel regions (CH1) of the write gates (121) and the source/drain regions of the write gates (112) (Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Choi and Yamazaki in view of Chen et al. such that the pocket well is located to contact the channel regions of the write gates and the source/drain regions of the write gates. Doing so would enhance programming efficiency and prevent short-channel effects.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 10355004 B2) in view of Yamazaki et al. (US 20220130844 A1), as applied to claim 1 above, in further view of Jin et al (US 20170154890 A1), Su et al. (US 20210242222 A1), and Chang et al. (US 20210384203 A1).
Regarding claim 5, Choi and Yamazaki are discussed above. Neither reference discloses the semiconductor substrate has a main cell array and a redundant cell array, wherein first word line connection lines connecting the write gates to the read gates and extending in a first direction are disposed in the main cell array, wherein second word line connection lines connecting the write gates to the read gates and extending in the first direction are disposed in the redundant cell array, and wherein each of the first word line connection lines and the second word line connection lines are not disposed in a straight line in the first direction.
However, Jin et al. disclose the semiconductor substrate has a main cell array (1000_1, Fig. 14) and a redundant cell array (1000_2, Fig. 14)
Su et al. disclose wherein first word line connection lines (WLP1, Fig. 2) connecting the write gates (112) to the read gates (110) and extending in a first direction (Y) are disposed in the main cell array, wherein second word line connection lines (WLR1, Fig. 2) connecting the write gates to the read gates and extending in the first direction are disposed in the redundant cell array
Jin et al. and Su et al. does not disclose wherein each of the first word line connection lines and the second word line connection lines are not disposed in a straight line in the first direction.
However, Chang et al. disclose wherein each of the first word line connection lines (240a, Fig. 2) and the second word line (240b, Fig. 2) connection lines are not disposed in a straight line in the first direction (patterned gate strips are not straight, paragraph 105).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Choi and Yamazaki in view of Jin, Su, and Chang such that the word line connection lines connecting the write gates to the read gates and extending in a first direction are disposed in the main cell array and redundant cell array, and the connection lines are not disposed in a straight line. Doing so would facilitate dual-mode operations and improve layout efficiency and density.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 10355004 B2) in view of Yamazaki et al. (US 20220130844 A1), Jin et al (US 20170154890 A1), Su et al. (US 20210242222 A1), and Chang et al. (US 20210384203 A1) as applied to claim 5 above, in further view of Kurjanowicz et al. (US 20120182782 A1) and Choi et al. (US 20150255469 A1).
Regarding claim 8, Choi, Yamazaki, Jin, Su, and Chang are discussed above. None of these references disclose dummy cells are arranged on both sides of each of the first word line connection lines, and the dummy cells are in a floating state.
However, Kurjanowicz et al. disclose dummy cells (2022, 2020, Fig. 29) are arranged on both sides of each of the first word line connection lines. It would have been obvious to one of ordinary skill in the art to replace the bit line BL of Kurjanowicz, Figure 29 with a word line to yield predictable results. In KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421 (2007).
Kurjanowicz et al. does not disclose the dummy cells are in a floating state.
However, Choi et al. (‘469) disclose the dummy cells are in a floating state (paragraph 269).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Choi, Yamazaki, Jin, Su and Chan in view of Kurjanowicz and Choi (‘469) such that the dummy gates are on both sides of a word line and are in a floating state. Doing so would prevent edge defects during manufacturing and to shield memory cells from electrical disturbances.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 10355004 B2) in view of Yamazaki et al. (US 20220130844 A1), Jin et al. (US 20170154890 A1), and Su et al. (US 20210242222 A1).
Regarding claim 11, Choi et al. disclose a one-time programmable (OTP) memory device comprising:
a semiconductor substrate (SUB, Fig. 2), wherein the main cell array and the redundant cell array each have a write region and a read region (WG and RG, Fig. 2, paragraph 6);
write gates disposed in the write region of the semiconductor substrate (WG on write region, Fig. 2, paragraph 6); read gates disposed in the read region of the semiconductor substrate (RG on read region, Fig. 2, paragraph 6);
a device isolation layer (ISO, Fig. 1) located between the write gates in the semiconductor substrate (Fig. 1);
wherein a pocket well (impurity well 99, Fig. 2) having the second conductivity type ((n-type, paragraph 42) is formed below the channel regions (formed in the write region of WG, Fig. 2) of the write gates.
However, Choi et al. does not disclose a main cell array and a redundant cell array, source/drain regions arranged adjacent to the write gates and the read gates in the semiconductor substrate; a bit line connected to the source/drain regions that are located between the read gates;
first word line connection lines connecting the write gates to the read gates in the main cell array and extending in a first direction; and second word line connection lines connecting the write gates to the read gates in the redundant cell array, and extending in the first direction, wherein the second word line connection lines are located in a corresponding region between the first word line connection lines, wherein channel regions are located below the write gates and the read gates and have a first conductivity type, wherein the source/drain regions have a second conductivity type, different from the first conductivity type.
However, Yamazaki et al. disclose the source/drain regions (source region 14 and drain region 13, Fig. 2) arranged adjacent to the write gates and the read gates (gate 16) and arranged in the semiconductor substrate (11, Fig. 2);
wherein, in the semiconductor substrate, channel regions (12) located below the write gates have a first conductivity type (channel region is integrated to substrate 11, which is p-type, paragraph 22),
wherein the source/drain regions (source 14 and drain 13, Fig. 2) have a second conductivity type (n-type, paragraph 27), different from the first conductivity type.
None of the prior references disclose a main cell array and a redundant cell array.
However, Jin et al. disclose a main cell array (1000_1) and a redundant cell array (1000_2) (Fig. 14).
None of the prior references disclose a bit line connected to the source/drain regions that are located between the read gates; first word line connection lines connecting the write gates to the read gates in the main cell array and extending in a first direction; and second word line connection lines connecting the write gates to the read gates in the redundant cell array, and extending in the first direction, wherein the second word line connection lines are located in a corresponding region between the first word line connection lines.
However, Su et al. disclose a bit line (BL) connected to the source/drain regions (104). Rearrangment of parts is within the routine skill level of one in the art. It would have been obvious to arrange the bit line such that it is between the read gates. In re Japikse, 181 F.2d 1019, 86 USPOQ70 (CCPA 1950). Su et al. also disclose a first word line (WLP1, Fig. 2) connection lines connecting the write gates (112) to the read gates (110) in the main cell array and extending in a first direction; and second word line (WLR1) connection lines connecting the write gates to the read gates in the redundant cell array, and extending in the first direction, wherein the second word line connection lines are located in a corresponding region between the first word line connection lines (can duplicate the layout to the redundant cell array, as shown in the reference Jin et al.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Choi, Yamazaki, and Jin in view of Su, such that the bit line is between the read gates, and connection lines connect the write gates to the read gates in the main cell array and duplicate cell array. Doing so would optimize speed, reliability, and allow for enable in-system programmability.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 10355004 B2) in view of Yamazaki et al. (US 20220130844 A1), Jin et al. (US 20170154890 A1), Su et al. (US 20210242222 A1) as applied to claim 11 above, in further view of Chen et al. (US 10090309 B1).
Regarding claim 12, Choi, Yamazaki, and X are discussed above. None of these references disclose the pocket well contacts the channel regions of the write gates and the source/drain regions of the write gates, and the first conductivity type is p-type, and the second conductivity type is n-type.
However, Chen et al. disclose the pocket well (131, 132, Fig. 2) contacts the channel regions (CH1) of the write gates (121) and the source/drain regions (112) of the write gates, and the first conductivity type is p-type, and the second conductivity type is n-type.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Choi, Yamazaki, Jin and Su in view of Chen et al. such that the pocket well is located to contact the channel regions of the write gates and the source/drain regions of the write gates. Doing so would enhance programming efficiency and prevent short-channel effects.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 10355004 B2) in view of Yamazaki et al. (US 20220130844 A1), Jin et al. (US 20170154890 A1), Su et al. (US 20210242222 A1), Kurjanowicz et al. (US 20120182782 A1), Kubota (US 20110108923 A1).
Regarding claim 16, Choi et al. disclose a one-time programmable (OTP) memory device comprising:
a semiconductor substrate including cell regions defined by device isolation layers (ISO, Fig. 1);
a write region and a read region located in each of the cell regions (WG, RG, Fig. 1);
a pair of write gates located in the write region of the cell region (WG on write region, Fig. 2, paragraph 6);
a pair of read gates arranged in the read region of the cell region (RG on read region, Fig. 2, paragraph 6) and located between the pair of write gates (read gates RG between write gates WG, Fig. 1);
Choi et al. do not disclose a main cell array and a redundant cell array, wherein the main cell array and the redundant cell array each have cell regions defined by device isolation layers; source/drain regions disposed adjacent to the pair of write gates and the pair of read gates and disposed in the semiconductor substrate; a bit line connected to the source/drain regions that are located between the pair of read gates on the semiconductor substrate; first word line connection lines connecting the write gates to the read gates of the cell regions and extending in a first direction in the main cell array; second word line connection lines connecting the write gates to the read gates of the cell regions, and extending in the first direction; and dummy cells arranged on both sides of each of the first word line connection lines and the second word line connection lines, wherein channel regions are located below each of the pair of write gates and the pair of read gates and have a first conductivity type, wherein the source/drain regions have a second conductivity type, different from the first conductivity type, and wherein a pocket well is disposed below the channel region of each of the pair of write gates and has the second conductivity type.
However, Yamazaki et al. disclose source/drain regions (13/14, Fig. 2) disposed adjacent to the pair of write gates (16) and the pair of read gates (56) and disposed in the semiconductor substrate (11); wherein the source/drain regions (source 14 and drain 13, Fig. 2) have a second conductivity type(n-type, paragraph 27), different from the first conductivity type.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Choi et al. in view of Yamazaki et al. such that the source/drain regions arranged adjacent to the write gates and the read gates and arranged in the semiconductor substrate; wherein, in the semiconductor substrate, channel regions located below the write gates have a first conductivity type, wherein the source/drain regions have a second conductivity type, different from the first conductivity type. Doing so would enable efficient, high-density, and low-power memory operation.
None of the prior references disclose a main cell array and a redundant cell array, wherein channel regions are located below each of the pair of write gates and the pair of read gates (120-T1) and have a first conductivity type.
However, Jin et al. disclose a main cell array (1000_1, Fig. 14) and a redundant cell array (1000_2, Fig. 14), and wherein channel regions (105, Fig, 1) are located below each of the pair of write gates (120-T0) and the pair of read gates (120-T1, Fig. 1) and have a first conductivity type (substrate area 102 is p-type, which is the same area as the channel region as shown in Fig. 1A).
None of the prior references disclose a bit line connected to the source/drain regions that are located between the read gates;
However, Su et al. disclose a bit line (BL) connected to the source/drain regions (104). Rearrangment of parts is within the routine skill level of one in the art. It would have been obvious to arrange the bit line such that it is between the read gates. In re Japikse, 181 F.2d 1019, 86 USPOQ70 (CCPA 1950). Su also discloses a first word line (WLP1, Fig. 2) connection lines connecting the write gates (112) to the read gates (110) of the cell regions and extending in a first direction in the main cell array; second word line (WLR1, Fig. 2) connection lines connecting the write gates to the read gates of the cell regions, and extending in the first direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Choi, Yamazaki, and Jin in view of Su, such that the bit line is between the read gates, and connection lines connect the write gates to the read gates. Doing so would optimize speed, reliability, and area efficiency of the device.
However, Kurjanowicz et al. disclose dummy cells (2022, 2020, Fig. 29) arranged on both sides of each of the first word line connection lines and the second word line connection lines. It would have been obvious to one of ordinary skill in the art to replace the bit line BL of Kurjanowicz, Figure 29 with a word line to yield predictable results. In KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421 (2007).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Choi, Yamazaki, Jin and Su in view of Kurjanowicz such that the dummy gates are on both sides of a word line. Doing so would prevent edge defects during manufacturing and to shield memory cells from electrical disturbances.
None of the prior references disclose wherein a pocket well is disposed below the channel region of each of the pair of write gates and has the second conductivity type.
However, Kubota et al. disclose wherein a pocket well (106, Fig. 1) is disposed below the channel region (112b) of each of the pair of write gates (116) and has the second conductivity type (paragraph 61).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Choi, Yamazaki, Jin, Su, Kurjanowicz, in view of Kubota such that a pocket well is disposed below the channel region of each of the pair of write gates and has the second conductivity type. Doing so would suppress short-channel effects and adjust the threshold voltage.
Regarding claim 19, Choi, Yamazaki, Jin, Su, Kurjanowicz, and Kubota are discussed above. Choi does not disclose a number of cell regions included in the main cell array is equal to a number of cell regions included in the redundant cell array.
However, Jin discloses a number of cell regions included in the main cell array (1000_1) is equal to a number of cell regions included in the redundant cell array (1000_2, Fig. 14) (tiny squares represent the cells, which are equal in both cell arrays based on Fig. 14).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Choi, Yamazaki, Su, Kurjanowicz, Kubota in view of Jin such that a number of cell regions included in the main cell array is equal to a number of cell regions included in the redundant cell array. Doing so would allow for 1-to-1 seamless address mapping.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 10355004 B2) in view of Yamazaki et al. (US 20220130844 A1), Jin et al. (US 20170154890 A1), Su et al. (US 20210242222 A1), Kurjanowicz et al. (US 20120182782 A1), and Kubota (US 20110108923 A1), as applied to claim 16 above, in further view of and Choi et al. (US 20150255469 A1).
Regarding claim 17, Choi, Yamazaki, Jin, Su, Kurjanowicz, and Kubota are discussed above. Choi discloses the semiconductor substrate has the first conductivity type (paragraph 60), wherein the first conductivity type is p-type, and the second conductivity type is n-type.
Choi does not disclose vertical level of a bottom surface of the device isolation layer is lower than a vertical level of a bottom surface of the pocket well, and dummy cells are in a floating state.
However, Jin discloses vertical level of a bottom surface of the device isolation layer (150, Fig. 1) is lower than a vertical level of a bottom surface of the pocket well (103h, Fig. 1).
However, Choi et al. (‘469) disclose the dummy cells are in a floating state (paragraph 269).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Choi, Yamazaki, Jin, Su, Kurjanowicz, and Kubota in view of Choi (‘469) such that a vertical level of a bottom surface of the device isolation layer is lower than a vertical level of a bottom surface of the pocket well, and the dummy cell is in floating state. Doing so would prevent leakage currents and optimize electrical isolation between memory cells.
Allowable Subject Matter
Claims 6-7, 9-10, 13-15, 18, 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE Q PHAN whose telephone number is (571)272-1227. The examiner can normally be reached Monday - Friday 8am - 5pm.
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/STEVE PHAN/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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