Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, in the reply filed on July 8, 2026, is acknowledged.
Claims 14-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on July 8, 2026.
Claim Objections
Claims 4 and 11 are objected to because of the following informalities:
In claim 4, lines 1-2, “in contact a side surface” should be “in contact with a side surface”.
In claim 11, lines 1-2, “in contact a side surface” should be “in contact with a side surface”.
Appropriate correction is required.
Applicant is advised that should claim 6 be found allowable, claim 8 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation, “an adjacent bottom FET of an adjacent contacted poly pitch (CPP).” It is unclear from the claims and from the specification what a contacted poly pitch is.
Claims 2-7 are dependent on claim 1 and therefore inherit the deficiencies of the parent claim.
Claim 8 recites the limitation, “an adjacent bottom FET of an adjacent contacted poly pitch (CPP).” It is unclear from the claims and from the specification what a contacted poly pitch is.
Claims 9-13 are dependent on claim 1 and therefore inherit the deficiencies of the parent claim.
It will be assumed for examination purposes that a contacted poly pitch is any pair of FETs, one in a top layer and one in a bottom layer, that form a “unit cell”.
This rejection can be overcome by defining in the specification or the claims what a contacted poly pitch is.
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Fig. 2A of Song, reproduced with annotations added by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-10, and 12-14 insofar, as in compliance with 112(b), are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Song et. al., Pub. No. US 2024/0355878, hereafter referred to as Song.
Regarding claim 1, Song teaches all of the limitations of the claim in Fig. 2A, reproduced above with annotations added by the examiner: “A semiconductor structure” (Fig. 2A) “comprising: a stacked field effect transistor (SFET)” ([0018]; Fig. 2A, lower transistor structure 200 and upper transistor structure 201) “comprising a top FET disposed over a bottom FET” (Fig. 2A, top FET/upper transistor structure 201 and bottom FET/lower transistor structure 200); “and a cross-couple connect (XCC), comprising an angled gate contact” ([0026]; Fig. 2A, lower portion of upper gate electrode 104 and intergate contact 108, hereafter referred to as the cross-couple connect (XCC); note that the intergate contact 108 has angled surfaces) “that connects a bottom surface of a top gate of the top FET” ([0026]; Fig. 2A, note that the XCC is connected to the remainder of the upper gate electrode 104) “to a top surface of a bottom gate of an adjacent bottom FET of an adjacent contacted poly pitch (CPP)” (Fig. 2A; note that the intergate contact 108 is connected to the lower gate electrode 204 in the adjacent unit cell to that consisting of the top FET and the bottom FET).
Regarding claim 2, Song further teaches “The semiconductor structure of claim 1, wherein the angled gate contact is disposed through a bonding dielectric between the top FET and the adjacent bottom FET” ([0028]; Fig. 2A, note that the lower portion of the upper gate electrode 104 is disposed within the second insulating layer 218 and the third insulating layer 220).
Regarding claim 3, Song further teaches “The semiconductor structure of claim 1, wherein a top S/D contact of the top FET is disposed over the angled gate contact” ([0035]: “In some embodiments… the upper source/drain region 106 may include metal layer(s) that include, for example, W, Al, Cu, Mo and/or Ru.”; it is assumed here that the metal layers function as source/drain contacts; also see Fig. 2A and note that, from the perspective indicated by the arrow added by the examiner, the source/drain contacts would appear to be above the intergate contact 108).
Regarding claim 5, Song further teaches “The semiconductor structure of claim 4, wherein there is no high-k gate dielectric disposed at sidewalls of a bottom gate of the adjacent bottom FET” ([0036]: “…the lower gate spacer 210 … may include, for example, … a low-k material.”; Fig. 2A, lower gate spacer 210).
Regarding claim 6, Song further teaches “The semiconductor structure of claim 1, wherein the angled gate contact is disposed over a non-active region of the semiconductor structure” ([0026] and [0028]; Fig. 2A; note that a portion of the intergate contact 108 is disposed on the first insulating layer 216).
Regarding claim 7, Song further teaches “The semiconductor structure of claim 1, wherein the semiconductor structure further includes the adjacent CPP” (Fig. 2A; note that the bottom FET of the adjacent unit cell is included within the semiconductor device).
Regarding claim 8, Song teaches all of the limitations of the claim in Fig. 2A, reproduced above with annotations added by the examiner: “A semiconductor structure” (Fig. 2A) “comprising: a stacked field effect transistor (SFET)” ([0018]; Fig. 2A, lower transistor structure 200 and upper transistor structure 201) “comprising a top FET disposed over a bottom FET” (Fig. 2A, top FET and bottom FET); “and a cross-couple connect (XCC), comprising an angled gate contact” ([0026]; Fig. 2A, lower portion of upper gate electrode 104 and intergate contact 108, hereafter referred to as the cross-couple connect (XCC); note that the intergate contact 108 has angled surfaces) “that connects a bottom surface of a top gate of the top FET” ([0026]; Fig. 2A, note that the XCC is connected to the remainder of the upper gate electrode 104) “to a top surface of a bottom gate of an adjacent bottom FET of an adjacent contacted poly pitch (CPP)” (Fig. 2A; note that the intergate contact 108 is connected to the lower gate electrode 204 in the adjacent unit cell to that consisting of the top FET and the bottom FET), “wherein the angled gate contact is disposed over a non-active region of the semiconductor structure” ([0026] and [0028]; Fig. 2A; note that a portion of the intergate contact 108 is disposed on the first insulating layer 216).
Regarding claim 9, Song further teaches “The semiconductor structure of claim 8, wherein the angled gate contact is disposed through a bonding dielectric between the top FET and the adjacent bottom FET” ([0028]; Fig. 2A, note that the lower portion of the upper gate electrode 104 is disposed within the second insulating layer 218 and the third insulating layer 220).
Regarding claim 10, Song further teaches “The semiconductor structure of claim 1, wherein a top S/D contact of the top FET is disposed over the angled gate contact” ([0035]; it is assumed here that the metal layers function as source/drain contacts; also see Fig. 2A and note that, from the perspective indicated by the arrow added by the examiner, the source/drain contacts would appear to be above the intergate contact 108).
Regarding claim 12, Song further teaches “The semiconductor structure of claim 8, wherein a high-k gate dielectric disposed at sidewalls of a bottom gate of the adjacent bottom FET” ([0036]: “…the lower gate spacer 210 … may include, for example, … silicon nitride.”; Fig. 2A, lower gate spacer 210).
Regarding claim 13, Song further teaches “The semiconductor structure of claim 8, wherein the semiconductor structure further includes the adjacent CPP” (Fig. 2A; note that the bottom FET of the adjacent unit cell is included within the semiconductor device).
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Fig. 5C of Natzle, reproduced with annotations added by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Natzle et. al., Pub. No. US 2004/0097047, hereafter referred to as Natzle.
Regarding claim 4, Song teaches “The semiconductor structure of claim 1” but does not teach “wherein the angled gate contact is in contact a side surface of the adjacent bottom FET.”
Natzle, on the other hand, teaches a transistor structure (Natzle Fig. 5C) with a gate electrode (Natzle [0035]; Fig. 5C, gate electrode 16), a gate encapsulation layer contacting the top and side surfaces of the gate electrode (Natzle [0080]: “In addition, the doped polysilicon, gate encapsulation layer 22G is also doped to provide a doped polysilicon coating of the gate electrode 16.”; Fig. 5C, gate encapsulation layer 22G), and a polysilicon cap (Natzle [0093]; Fig. 5C, polysilicon cap 25C). Note that the latter two elements, the gate encapsulation layer and the polysilicon cap, can be regarded as a gate contact.
The contact between the gate encapsulation layer and the top and side surfaces of the gate electrode taught by Natzle can be incorporated into the device of Song by having the intergate contact extend downwards to also contact side surfaces of the lower gate electrode. The combined device teaches “wherein the angled gate contact is in contact a side surface of the adjacent bottom FET” (Song [0026]; Fig. 2A, intergate contact 108; Natzle [0080]; Fig. 5C, gate encapsulation layer 22G; note that the intergate contact 108 of Song covers side surfaces of the lower gate electrode 204 in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have extended the intergate contact of Song so that it also contacts the side surfaces of the lower gate electrode as suggested by Natzle because doing so would increase the contact area and thus decrease resistance and it would be a simple combination of elements of the two disclosures.
Regarding claim 11, Song teaches “The semiconductor structure of claim 8” but does not teach “wherein the angled gate contact is in contact a side surface of the adjacent bottom FET.”
Natzle, on the other hand, teaches a transistor structure (Natzle Fig. 5C) with a gate electrode (Natzle [0035]; Fig. 5C, gate electrode 16), a gate encapsulation layer contacting the top and side surfaces of the gate electrode (Natzle [0080]: “In addition, the doped polysilicon, gate encapsulation layer 22G is also doped to provide a doped polysilicon coating of the gate electrode 16.”; Fig. 5C, gate encapsulation layer 22G), and a polysilicon cap (Natzle [0093]; Fig. 5C, polysilicon cap 25C). Note that the latter two elements, the gate encapsulation layer and the polysilicon cap, can be regarded as a gate contact.
The contact between the gate encapsulation layer and the top and side surfaces of the gate electrode taught by Natzle can be incorporated into the device of Song by having the intergate contact extend downwards to also contact side surfaces of the lower gate electrode. The combined device teaches “wherein the angled gate contact is in contact a side surface of the adjacent bottom FET” (Song [0026]; Fig. 2A, intergate contact 108; Natzle [0080]; Fig. 5C, gate encapsulation layer 22G; note that the intergate contact 108 of Song covers side surfaces of the lower gate electrode 204 in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have extended the intergate contact of Song so that it also contacts the side surfaces of the lower gate electrode as suggested by Natzle because doing so would increase the contact area and thus decrease resistance and it would be a simple combination of elements of the two disclosures.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Robert E Throckmorton whose telephone number is (571) 272-7014. The examiner can normally be reached 7:30 AM - 11:30 AM and 12:30 PM - 4:30 PM ET Monday to Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H Loke can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.E.T./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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