Prosecution Insights
Last updated: October 23, 2026
Application No. 18/614,151

ELECTRONIC PART

Non-Final OA §102§103
Filed
Mar 22, 2024
Priority
Mar 27, 2023 — JP 2023-050132
Examiner
STUART, RAMSEY LANE
Art Unit
2831
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Rohm Co., Ltd.
OA Round
1 (Non-Final)
Grant Probability
Favorable
1-2
OA Rounds

Examiner Intelligence

Grants only 0% of cases
0%
Career Allowance Rate
0 granted / 0 resolved
-68.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
Avg Prosecution
3 currently pending
Career history
3
Total Applications
across all art units
This examiner has no resolved cases yet (career too new); statute-level performance unavailable. The Grant Probability card shows Tech Center averages instead.

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: "ELECTRONIC PART COMPRISING A RESISTOR ARRAY". The disclosure is objected to because of the following informalities: Para. 42/L7, the sentence should end with a period. Para. 56/L12, the phrase “resistance values of the” appears to be repeated. It is recommended to remove the second instance of the phrase: “…and the resistance values of the Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Akiyoshi (JP 2014053413 A) hereinafter referred to as “Akiyoshi”. Regarding claim 1, Akiyoshi discloses an electronic part, (Abstract) comprising: a substrate, having a first main surface; (Para. 12/L6, a semiconductor integrated circuit implies a base substrate) a first external terminal and a second external terminal, formed on the first main surface and spaced apart from each other; (Para. 13/L5-6) and a resistive circuit portion, formed on the first main surface and electrically connected to the first external terminal and the second external terminal, (Para. 12/L4-5) wherein the resistive circuit portion includes: a first wiring, formed on the first main surface and to which the first external terminal is electrically connected; (Para. 13/L2-3, Fig. 2 Element L1) a second wiring, formed on the first main surface and electrically connected to the second external terminal; (Para. 13/L4-5, Fig. 2 Element L2) and a first resistor unit and a second resistor unit that are electrically connected to the first wiring and the second wiring, extend along a first direction in a plan view (Para. 13, Fig. 2, R5-8 is the first resistor unit, b1-4 is the second resistor unit. The first direction is perpendicular to the wirings L1 and L2.) and are arranged along a second direction orthogonal to the first direction, wherein a length of the second resistor unit along the first direction is less than a length of the first resistor unit along the first direction. (Para. 13, Fig. 2, the second direction is parallel to the wirings L1 and L2, and resistors b1-4 are shorter in the first direction because part of their length is replaced by the fuses a1-4) Regarding claim 10, Akiyoshi teaches the electronic part of claim 1 as discussed above and discloses said electronic part is a chip resistor. (Para. 13/L5-7, an IC package consisting of resistors is a chip resistor.) Claims 1, 4 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by King (US 3983528 A) hereinafter referred to as “King”. Regarding claim 1, King discloses an electronic part, (Abstract) comprising: a substrate, having a first main surface; (C2/L3-5, Fig. 1 Element 1) a first external terminal and a second external terminal, formed on the first main surface and spaced apart from each other; (C2/L7-8, Fig. 1 Element 4, The left post 4 is the first terminal and the right post 4 is the second terminal) and a resistive circuit portion, formed on the first main surface and electrically connected to the first external terminal and the second external terminal, (C2/L5-8, Fig. 1 Elements 2 and 3) wherein the resistive circuit portion includes: a first wiring, formed on the first main surface and to which the first external terminal is electrically connected; (C2/L5-7, Fig. 1 Left half of element 3) a second wiring, formed on the first main surface and electrically connected to the second external terminal; (C2/L5-7, Fig. 1 Right half of element 3) and a first resistor unit and a second resistor unit that are electrically connected to the first wiring and the second wiring, extend along a first direction in a plan view (C2/L5-7, Fig. 1 Element 2, The resistor 2 closest to and inseparably connected to the terminals 4 is the second resistor unit, and the remaining 10 resistors 2 separably connected to the terminals 4 are the first resistor unit. The first direction is parallel to the long side of the conductive strip 3.) and are arranged along a second direction orthogonal to the first direction, wherein a length of the second resistor unit along the first direction is less than a length of the first resistor unit along the first direction. (Fig. 1 Elements 2, with the first and second resistor unit as described above.) Regarding claim 4, King further discloses the first resistor unit is a correction resistor unit that is electrically separably connected to the first wiring and the second wiring, (C2/L8-18, Fig. 1 Element 5) and the second resistor unit is a main resistor unit that is electrically inseparably connected to the first wiring and the second wiring. (Fig. 1 Resistor 2, the second resistor unit described above does not have a weakened line 5 to potentially break its connection to the terminals) Regarding claim 13, King discloses the electronic part of claim 4 as discussed above, and discloses the electronic part is a chip resistor. (C1/L35-40, a resistor network for use in electronic circuits is a resistor chip) Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Akiyoshi in view of Cao et al. (US 10274876 B2), hereinafter referred to as "Cao". Regarding claim 2, Akiyoshi teaches the electronic part of claim 1 as discussed above. Akiyoshi does not teach the specific length difference detailed further in claim 2. However, Cao et al. discloses the length of the second resistor unit along the first direction is between about 1/2 and about 3/4 of the length of the first resistor unit along the first direction. (C5/L50-55 Fig. 3 Elements 304 and 306) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to substitute the resistive strips of Akiyoshi with the resistive strips of Cao et al. The first direction would be perpendicular to the long side of resistive strips 304 and 306, and the second direction would be along the long side of the resistive strips. They would be motivated to make this substitution to heat a smaller area of a heating nib for low-speed printing, and a larger area for high-speed printing, as taught by Cao et al. (C7/L56-C8/L13) Regarding claim 11, Akiyoshi in view of Cao et al. teaches the electronic part of claim 2 as discussed above. Additionally, Akiyoshi discloses the electronic part is a chip resistor. (Para. 13/L5-7, an IC package consisting of resistors is a chip resistor.) Claims 3, 8, 12 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Akiyoshi in view of Coolbaugh et al. (US 7300807 B2), hereinafter referred to as "Coolbaugh". Regarding claim 3, Akiyoshi teaches the electronic part of claim 1 as discussed above and discloses the first resistor unit is a main resistor unit that is electrically inseparably connected to the first wiring and the second wiring. (Para. 14/L5-7, Fig. 2 Elements R5-8 are inseparable because they do not have a thinned fuse portion.) Akiyoshi does not teach that the second resistor unit is separably connected to both the first and second wiring. However, Coolbaugh et al. discloses the second resistor unit is a correction resistor unit that is electrically separably connected to the first wiring and the second wiring. (Col. 5/L46-51, Fig. 2) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to shorten the second wiring L2 where it connects to b1-4 and replace it with thinner segments matching a1-4. They would have been motivated to make such a modification to have no excess capacitance from broken fuses, as taught by Coolbaugh (Col. 2/L34-37). Regarding claim 8, the electronic part of claim 3 is taught by Akiyoshi in view of Coolbaugh et al., as discussed above. Akiyoshi also discloses that the resistive circuit portion includes: a first fuse, connecting the correction resistor unit and the first wiring in a separable manner. (Fig. 2 Elements a1-4, Para. 24) Akiyoshi does not teach that the correction resistor unit is also separably connected to the second wiring, as detailed in claim 8. However, Coolbaugh et al. discloses a second fuse, connecting the correction resistor unit and the second wiring in a separable manner. (Col. 5/L46-51, Fig. 2) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to shorten the second wiring L2 where it connects to b1-4 and replace it with thinner segments matching a1-4. They would have been motivated to make such a modification to have no excess capacitance from broken fuses, as taught by Coolbaugh (Col. 2/L34-37). Regarding claims 12 and 17, Akiyoshi further discloses the electronic part is a chip resistor. (Para. 13/L5-7, an IC package consisting of resistors is a chip resistor.) Claims 5-7 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Akiyoshi and Coolbaugh as applied to claim 3 above, and further in view of Tsumura (WO 2014041950 A1), hereinafter referred to as "Tsumura". Regarding claims 5-7, Akiyoshi also discloses that the correction resistor unit includes a first correction resistor, a second correction resistor and a third correction resistor that are adjacent to each other along the second direction, (Fig. 2 Elements b2-4) the first correction resistor, the second correction resistor and the third correction resistor are arranged in an order and toward a side away from the first resistor unit along the second direction. (Fig. 2 Elements b2-4, b4 is first, b3 is second, b2 is third) Akiyoshi does not teach the particular variation in width of the resistors further detailed in claims 5-7. However, Tsumura discloses a width of the second correction resistor along the second direction is less than a width of the first correction resistor along the second direction, (Fig. 5 Elements 1/4R, 1/2R, 1R) and a width of the third correction resistor along the second direction is less than the width of the second correction resistor along the second direction. (Fig. 5 Elements 1/4R, 1/2R, 1R) Tsumura also discloses a width of the main resistor unit along the second direction is greater than the width of the first correction resistor along the second direction, the width of the second correction resistor along the second direction, and the width of the third correction resistor along the second direction. (Fig. 5 Elements 1/16R and 1/8R are the main resistor unit, which is wider than 1/4R, 1/2R, and 1R.) Additionally, Tsumura discloses that a width of the main resistor unit along the second direction is greater than a length of the main resistor unit along the first direction. (Fig. 5 Elements 1/16R and 1/8R) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to substitute the resistors of Akiyoshi R6, R5, b4, b3, and b2 with the resistors of Tsumura 1/16R, 1/8R, 1/4R, 1/2R, and 1R, respectively. They would have been motivated to make such a substitution to change the range and/or step size of the resistance value as individual resistor fuses are broken as taught by Akiyoshi (Para. 42/L3-5). They would have been motivated to use the resistors of Tsumura specifically to increase accuracy of the resistor values as taught by Tsumura. (C5/L33-40) Regarding claims 14-16, the electronic part of claims 5, 6, and 7 are taught by Akiyoshi in view of Coolbaugh and Tsumura as discussed above. Additionally, Akiyoshi discloses that the electronic part is a chip resistor. (Para. 13/L5-7, an IC package consisting of resistors is a chip resistor.) Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Akiyoshi in view of Niiyama (US 20150162327 A1) hereinafter referred to as "Niiyama". Regarding claim 9, Akiyoshi teaches the electronic part of claim 1 as discussed above but does not teach the element stack further detailed in claim 9. However, Niiyama discloses a resistor array comprising an element stack portion, including a resistive film formed on the first main surface (Para. 73, Fig. 7 Element 232) and a first conductive film formed on the resistive film, (Para. 73, Fig. 7 Element 233) wherein the first conductive film includes the first wiring and the second wiring physically separated from the first wiring, (Para. 77, 79, Fig. 5 Elements 234 and 22) and the first resistor unit and the second resistor unit are formed by a portion of the resistive film exposed from the first conductive film in a region between the first wiring and the second wiring. (Para. 74, Fig. 7 Element 231) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to construct the electronic part of Akiyoshi using the layer structure of Niiyama. They would have been motivated to construct the chip in that way to make the part small and precisely set the resistance, as taught by Niiyama. (Para. 87) Regarding claim 18, Akiyoshi in view of Niiyama teaches the electronic part of claim 9 as discussed above. Additionally, Akiyoshi also teaches the electronic part is a chip resistor. (Para. 13/L5-7, an IC package consisting of resistors is a chip resistor.) Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAMSEY LANE STUART whose telephone number is (571)272-0507. The examiner can normally be reached Mon-Fri 9:00-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Renee Luebke can be reached at (571)272-2009. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Ramsey Lane Stuart/ Examiner, Art Unit 2831 /renee s luebke/ Supervisory Patent Examiner Art Unit 2831
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Prosecution Timeline

Mar 22, 2024
Application Filed
Sep 29, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
Grant Probability
Low
PTA Risk
Based on 0 resolved cases by this examiner. Grant probability derived from career allowance rate.

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