Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the application filed on or reply to the remarks of 2/16/2026. The instant application has claims 1-20 pending. The system and method for providing an protection circuit for resource isolation after having an alert of potential anomalies. There a total of 20 claims.
Response to Arguments
Applicant's arguments filed 2/16/2026 have been fully considered but they are not persuasive.
The applicant argues that double patenting rejection is not relevant in view of current amendments.
The examiner respectfully disagrees. The claims are still obvious over the ‘812 patent application. The steps are similar, the goal is similar and elements involved are similar.
The applicant further argues that interconnection bus between protection circuit and slave resource that is configured to generate an alert to countermeasure circuit bypassing the interconnection bus.
Ahmad discloses the protection circuit for checking if access is authorized and error handling see Col 14 Ln 10-63. And when it is determined poisoned access request is made then the bus is multiplexed to divert from access to memory and error handling rules are used is see Fig. 11 item 1102-1116 & Col 1 Ln 52-61 & Col 2 Ln 50-Col 3 Ln 3 & Col 7 Ln 32-53.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent App # 18514812 Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are an broader version of claims of ‘812 application, i.e. the instant claims are anticipated by ‘812 application claims.
US App # 18614171
US App # 18/514812
Comments
1. A system-on-a-chip comprising: at least one slave resource; a resource isolation system comprising, in a set of configuration registers, for each at least one slave resource, a first location for containing an alert parameterization datum; a countermeasure circuit configured to limit an operation of the system-on-a-chip in response to potential anomalies; and for each at least one slave resource, a protection circuit configured to: block or transmit a transaction addressed to the at least one slave resource depending on access rights of the at least one slave resource and of the transaction; and generate and directly communicate an alert signal to the countermeasure circuit in response to the transaction being blocked, according to the alert parameterization datum for the at least one slave resource.
1. A system-on-chip (SoC), comprising: a primary circuit; an auxiliary resource; an interconnection bus comprising an error notification channel, the interconnection bus configured to couple the primary circuit to the auxiliary resource; and a resource isolation system comprising a protection circuit for the auxiliary resource, the protection circuit configured to: transmit or block a transaction addressed to the auxiliary resource via the interconnection bus in accordance with access rights of the auxiliary resource and the transaction, and generate, on the error notification channel, a notification signal in response to the protection circuit blocking the transaction.
Both claims recites the similar subject matter and steps of providing an isolation of resources based on notification of potential anomalies. It would have been obvious at the time of filing to include modify the transaction addressed to auxiliary resource in ‘812 application to an slave resources with access rights and error notification of ‘812 application to potential anomalies.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent 9213866 to Ahmad in view of US Patent 8209565 to Akaike.
Regarding claim 1, 7, 16, Ahmad discloses A system-on-a-chip comprising: an interconnection bus(Fig. 7 & Fig. 1 item 104 control circuit to memory & control circuit to programmable resource); at least one slave resource(Col 2 Ln 50-Col 3 Ln 3); a resource isolation system comprising, in a set of configuration registers, for each at least one slave resource, a first location for containing an alert parameterization datum(Abstract &Fig. 9 item 902-908, the circuit blocks are protected with protection blocks and an unauthorized access is detected & Fig. 11 item 1114) ; a countermeasure circuit configured to limit an operation of the system-on-a-chip in response to potential anomalies(Fig. 9 item 908 & Fig. 10 & Col 3 Ln 4-23) ; and for each at least one slave resource, a protection circuit coupled between the at least one slave resource and the interconnection bus, and configured to: block or transmit a transaction addressed to the at least one slave resource depending on access rights of the at least one slave resource and of the transaction(Fig. 11 item 11102, 1112 the access permissions & Col 5 Ln 23-45 & Fig. 11 item 1102-1116 & Col 1 Ln 52-61 & Col 2 Ln 50-Col 3 Ln 3 & Col 7 Ln 32-53).
Ahmad does not disclose generate and directly communicate an alert signal to the countermeasure circuit in response to the transaction being blocked, according to the alert parameterization datum for the at least one slave resource.
In the same field of endeavor as the claimed invention, Akaike discloses generate and directly communicate an alert signal to the countermeasure circuit, bypassing the interconnection bus, in response to the transaction being blocked, according to the alert parameterization datum for the at least one slave resource(Abstract & Fig. 5 item 19, 20, 18 & Col 2 Ln 11-48, the notification about error results the disabling and blocking access to bus).
It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to modify Ahmad invention to incorporate generate and directly communicate an alert signal to the countermeasure circuit in response to the transaction being blocked, according to the alert parameterization datum for the at least one slave resource for the advantage of preventing protection against error states being loaded as taught in Col 2 Ln19-30
Regarding claim 2, 9 The combined system of Ahmad and Akaike, Ahmad discloses the system-on-a-chip according to claim 1, further comprising a respective alert channel directly connecting the protection circuit of each at least one slave resource to the countermeasure circuit and dedicated to transmission of the alert signal(Col 5 Ln 10-46, permissions are checked and poisoned alerts are provided)
Regarding claim 3, 10, The combined system of Ahmad and Akaike, Ahmad discloses the system-on-a-chip according to claim 2, further comprising: a plurality of the at least one slave resource; and a multiplexing element configured to group all of the alert channels respectively connected to each respective protection circuit into a single outgoing alert channel directly connected to the countermeasure circuit(Col 5 Ln 38-46, the de-multiplexing).
Regarding claim 4, 11, The combined system of Ahmad and Akaike, Ahmad discloses the system-on-a-chip according to claim 3, wherein the multiplexing element has an "OR gate"-type function for grouping the alert channels(Col 4 Ln 4-17, the ASIC has OR gates).
Regarding claim 5. The combined system of Ahmad and Akaike, Ahmad discloses the system-on-a-chip according to claim 1, wherein: the system-on-a-chip further comprises at least one master device configured to generate the transaction addressed to the at least one slave resource comprising a master identification datum; the resource isolation system comprises, in the set of configuration registers, for each master device, a second location for containing a second alert parameterization datum; and the protection circuit of each at least one slave resource is configured to generate, or not, the alert signal in response to the transaction addressed to the at least one slave resource by the master device being blocked, according to the second alert parameterization datum for the at least one master device(Col 2 Ln 50- Col 3 Ln 23).
Regarding claim 6. The combined system of Ahmad and Akaike, Ahmad discloses the system-on-a-chip according to claim 1, wherein the protection circuit, for each at least one slave resource, is further configured to: refrain from generating and communicating the alert signal to the countermeasure circuit in response to the transaction being blocked, according to the alert parameterization datum for the at least one slave resource(Fig. 11 item 1116, request is poisoned).
Regarding claim 8. the combined method of Ahmad and Akaike, Ahmad discloses the method according to claim 7, further comprising: blocking, by the protection circuit, a second transaction addressed to a second slave resource of the at least one slave resource, based on the access rights of the second slave resource and of the second transaction; and refraining from generating a second alert signal in response to the second transaction being blocked, according to the alert parameterization datum for the second slave resource( Col 2 Ln 50- Col 3 Ln 23, access rights are checked for access).
Regarding claim 12. the combined method of Ahmad and Akaike, Ahmad discloses the method according to claim 11, wherein the combined method of Ahmad and Akaike, Ahmad discloses the method further comprises: transmitting, by the protection circuit, a second transaction addressed to the at least one slave resource according to the alert parameterization datum for the at least one slave resource(Col 8 Ln 1-19, the registers and data is checked).
Regarding claim 13. the combined method of Ahmad and Akaike, Ahmad discloses the method according to claim 12, wherein the system-on-a-chip further comprises at least one master device, and a second alert parameterization datum for each master device is contained in the set of configuration registers, and the combined method of Ahmad and Akaike, Ahmad discloses the method further comprises: generating, by the at least one master device, the first transaction addressed to the at least one slave resource comprising an identification datum for the master device(Col 7 Ln 1-53) ; and generating the alert signal in response to the first transaction addressed to the at least one slave resource by the master device being blocked, according to the second alert parameterization datum for the at least one master device(Col 7 Ln 1-53).
Regarding claim 14. the combined method of Ahmad and Akaike, Ahmad discloses the method according to claim 13, wherein the method further comprises: generating, by the at least one master device, a third transaction addressed to the at least one slave resource comprising the identification datum for the master device; and transmitting, by the protection circuit, the third transaction addressed to the at least one slave resource, based on the second alert parameterization datum for the at least one master device(Col 7 Ln 1-53). .
Regarding claim 15. the combined method of Ahmad and Akaike, Ahmad discloses the method according to claim 7, further comprising transmitting, by the protection circuit, a second transaction addressed to the at least one slave resource, based on the access rights of the at least one slave resource and of the second transaction(Col 2 Ln 50- Col 3 Ln 23).
Regarding claim 16. Ahmad discloses A system-on-a-chip comprising: an interconnection bus(Fig. 7 & Fig. 1 item 104 control circuit to memory & control circuit to programmable resource); a first slave resource(Fig. 9 item 902, circuit blocks); a second slave resource(Fig. 9 item 902, circuit blocks); a resource isolation system comprising, in a set of configuration registers, a first location for containing a first alert parameterization datum for the first slave resource(Fig. 10 item 1006, 1008 & Fig. 11 item 1114, 1116); a countermeasure circuit configured to limit an operation of the system-on-a-chip in response to potential anomalies(Col 5 Ln 23-46, the protection circuits & Fig. 9 item 906-908); a first protection circuit for the first slave resource, wherein the first protection circuit is coupled between the at least one first slave resource and the interconnection bus, and configured to depending on first access rights of the first slave resource and of the first transaction(Col 5 Ln 23-46, the protection circuits & Col 6 Ln 33-67); and generate and directly communicate a first alert signal to the countermeasure circuit, bypassing the interconnection bus, in response to the first transaction being blocked, according to the first alert parameterization datum for the first slave resource(Fig.11 item 1110-1116); and a second protection circuit for the second slave resource, wherein the second protection circuit coupled between the at least one second slave resource and the interconnection bus, and configured to block or transmit a first and second transaction depending on second access rights of the second slave resource and of the second transaction (Col 5 Ln 23-46, the protection circuits & Col 6 Ln 33-67 & Fig. 11 item 1102-1116 & Col 1 Ln 52-61 & Col 2 Ln 50-Col 3 Ln 3 & Col 7 Ln 32-53); and generate and directly communicate a second alert signal to the countermeasure circuit, bypassing the interconnection bus, in response to the second transaction being blocked(Fig. 9 item 908).
Ahmad does not discloses send alerts by first protection circuit or second protection circuit.
In the same field of endeavor as the claimed invention, Akaike discloses first and second protection circuit to send alerts b (Abstract & Fig. 5 item 19, 20, 18 & Col 2 Ln 11-48, the notification about error results the disabling and blocking access to bus).
It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to modify Ahmad invention to incorporate generate and directly communicate an alert signal to the countermeasure circuit in response to the transaction being blocked, according to the alert parameterization datum for the at least one slave resource for the advantage of preventing protection against error states being loaded as taught in Col 2 Ln19-30
Regarding claim 17. The combined system of Ahmad and Akaike, Ahmad discloses the system-on-a-chip according to claim 16, further comprising first and second alert channels directly connecting the first and second protection circuits respectively, to the countermeasure circuit and dedicated to transmission of the first and second alert signals, respectively(Col 2 Ln 50- Col 3 Ln 23). .
Regarding claim 18. The combined system of Ahmad and Akaike, Ahmad discloses the system-on-a-chip according to claim 17, further comprising: a multiplexing element configured to group the first and second alert channels into a single outgoing alert channel directly connected to the countermeasure circuit(Col 2 Ln 50- Col 3 Ln 23, alerts). .
Regarding claim 19. The combined system of Ahmad and Akaike, Ahmad discloses the system-on-a-chip according to claim 16, wherein: the resource isolation system comprises, in the set of configuration registers, a second location for containing a second alert parameterization datum for the second slave resource (Col 8 Ln 1-19, the registers and data is checked); and the second protection circuit is configured to generate, or not, the second alert signal in response to the second transaction addressed to the second slave resource being blocked, according to the second alert parameterization datum for the second slave resource(Col 8 Ln 1-19, the registers and data is checked).
Regarding claim 20. The combined system of Ahmad and Akaike, Ahmad discloses the system-on-a-chip according to claim 19, wherein: the system-on-a-chip further comprises: a first master device configured to generate the first transaction addressed to the first slave resource comprising a first master identification datum(Col 2 Ln 50- Col 3 Ln 23 & Fig. 11 item 1102, master ID); a second master device configured to generate the second transaction addressed to the second slave resource comprising a second master identification datum(Col 2 Ln 50- Col 3 Ln 23 & Fig. 11 item 1102, master ID). ; the resource isolation system comprises, in the set of configuration registers: a third location for containing a third alert parameterization datum for the first master device(Col 2 Ln 50- Col 3 Ln 23 & Fig. 2 item 120, 122,114) ; and a fourth location for containing a fourth alert parameterization datum for the second master device(Col 2 Ln 50- Col 3 Ln 23, alerts) ; the first protection circuit is configured to generate, or not, the first alert signal in response to the first transaction addressed to the first slave resource by the first master device being blocked, according to the third alert parameterization datum for the first master device(Fig. 2 item 226); and the second protection circuit is configured to generate, or not, the second alert signal in response to the second transaction addressed to the second slave resource by the second master device being blocked, according to the fourth alert parameterization datum for the second master device(Col 2 Ln 50- Col 3 Ln 23, alerts and blocking). .
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Venkat Perungavoor whose telephone number is (571)272-7213. The examiner can normally be reached 9-5.
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/VENKAT PERUNGAVOOR/Primary Examiner, Art Unit 2492 Email: venkatanarayan.perungavoor@uspto.gov
Prosecution Insights