CTNF 18/614,290 CTNF 73834 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This Office Action is in response to the application filed March 22, 2024. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-8 and 10 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Zhou et al. (US 10,490,667 B1) . In regard to claim 1, Zhou et al. (US 10,490,667 B1) teach an integrated circuit structure, comprising: a backbone 280; a first transistor device 310 comprising a first semiconductor channel 130 adjacent to an edge of the backbone 280; and a second transistor device 300 comprising a second semiconductor channel 170 adjacent to the edge of the backbone 280, the second transistor device 300 stacked on the first transistor device 310 (Figures 2-13 and 15, columns 8-15, lines 44-67, 1-67, 1-67, 1-67, 1-67, 1-67, 1-67 and 1-57, respectively). In regard to claim 2, Zhou et al. teach the first transistor device 310 comprising one or more additional semiconductor channels 130 (See Figure 11) (Figures 2-13 and 15, columns 8-15, lines 44-67, 1-67, 1-67, 1-67, 1-67, 1-67, 1-67 and 1-57, respectively). In regard to claim 3, Zhou et al. teach the second transistor device 310 comprising one or more additional semiconductor channels 170 (See Figure 11) (Figures 2-13 and 15, columns 8-15, lines 44-67, 1-67, 1-67, 1-67, 1-67, 1-67, 1-67 and 1-57, respectively). In regard to claim 4, Zhou et al. teach the first transistor device 310 being a P-type device, and the second transistor device 300 being an N-type device (Figures 2-13 and 15, columns 8-15, lines 44-67, 1-67, 1-67, 1-67, 1-67, 1-67, 1-67 and 1-57, respectively). In regard to claim 5, Zhou et al. teach the first transistor device 310 being an N-type device, and the second transistor device 300 being a P-type device (Figures 2-13 and 15, columns 8-15, lines 44-67, 1-67, 1-67, 1-67, 1-67, 1-67, 1-67 and 1-57, respectively). In regard to claim 6, Zhou et al. teach the first and second semiconductor channels 130/170 being first and second nanowires (Figures 2-13 and 15, columns 8-15, lines 44-67, 1-67, 1-67, 1-67, 1-67, 1-67, 1-67 and 1-57, respectively). In regard to claim 7, Zhou et al. teach the first and second semiconductor channels 130/170 being first and second nanoribbons (Figures 2-13 and 15, columns 8-15, lines 44-67, 1-67, 1-67, 1-67, 1-67, 1-67, 1-67 and 1-57, respectively). In regard to claim 8, Zhou et al. teach a first gate structure 210/230 on the first semiconductor channel 130, the first gate structure 210/230 comprising a first gate electrode 230 and a first gate dielectric 210; and a second gate structure 210/230 on the second semiconductor channel 170, the second gate structure 210/230 comprising a second gate electrode 230 and a second gate dielectric 210 (Figures 2-13 and 15, columns 8-15, lines 44-67, 1-67, 1-67, 1-67, 1-67, 1-67, 1-67 and 1-57, respectively). In regard to claim 10, Zhou et al. teach the first gate electrode 230 (of 310) separated from the second gate electrode 230 (of 300) by a dielectric layer 155 (Figures 2-13 and 15, columns 8-15, lines 44-67, 1-67, 1-67, 1-67, 1-67, 1-67, 1-67 and 1-57, respectively) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 12-151-07 AIA 07-97 12-51-07 Claim s 11-20 are allowed. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: The prior art of record (Zhou et al. (US 10,490,667 B1)) does not disclose, make obvious, or otherwise suggest the structure of the applicant's claimed invention together with the other limitations of the dependent claims 12-20, such as the configuration of the computing device comprising: a board, component, backbone, transistor devices, semiconductor channels and backbone edge . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to integrated circuit structures: Ando et al. (US 10,332,809 B1) Cheng et al. (US 2015/0263088 A1) Dewey et al. (US 2020/0105751 A1) Smith et al. (US 2019/0172755 A1) Zhang et al. (US 2019/0121396 A1). Any inquiry concerning this communication or earlier communications from the examiner should be directed to IDA M SOWARD whose telephone number is (571)272-1845. The examiner can normally be reached Monday through Thursday, 7am to 5:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. IMS May 5, 2026 /IDA M SOWARD/Primary Examiner, Art Unit 2898 Application/Control Number: 18/614,290 Page 2 Art Unit: 2898 Application/Control Number: 18/614,290 Page 3 Art Unit: 2898 Application/Control Number: 18/614,290 Page 4 Art Unit: 2898 Application/Control Number: 18/614,290 Page 5 Art Unit: 2898 Application/Control Number: 18/614,290 Page 6 Art Unit: 2898
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