Prosecution Insights
Last updated: July 17, 2026
Application No. 18/614,454

PHASE INVARIANT VARIABLE GAIN AMPLIFIER FOR A WIRELESS SYSTEM

Non-Final OA §103
Filed
Mar 22, 2024
Priority
Mar 22, 2023 — provisional 63/453,973
Examiner
RAHMAN, HAFIZUR
Art Unit
Tech Center
Assignee
BDCM A2 LLC
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
686 granted / 734 resolved
+33.5% vs TC avg
Moderate +8% lift
Without
With
+8.4%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
44 currently pending
Career history
764
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
68.9%
+28.9% vs TC avg
§102
16.7%
-23.3% vs TC avg
§112
9.5%
-30.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 734 resolved cases

Office Action

§103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Note Regarding CN 223639245 U (Li) Li successfully discloses every limitation of the independent claims 1, 8, and 12, including the complementary bias control of parallel sets of main and cross-coupled transistors to achieve vector synthesis phase control. However, because Li's publication date is December 5, 2025, which falls after the application's priority date of March 22, 2023, it does not qualify as valid prior art under 35 U.S.C. § 102 or § 103 and cannot be used to reject these claims. Because Li is disqualified by its date, a 35 U.S.C. § 102 anticipation rejection cannot be maintained across all three claims from a single prior art reference. However, 103 rejection follows: Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1, 8 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Cui (US 2022/0021363 A1) in view of Ibrahim (US 11,277,108 B1). PNG media_image1.png 409 483 media_image1.png Greyscale Fig. 1 of Cui: An active VGA of a cascade structure. Regarding Claims 1,8 and 12: Cui teaches a variable gain amplifier (which operates as a programmable amplifier) comprising a first set of transistors (M₂) (FIG. 1) coupled to a first bias voltage, and a second set of transistors (M₁) (FIG. 1) coupled to a second bias voltage (Gain_T). The second set is coupled in parallel with the first set (FIG. 1). Cui teaches a control module adapted to control the bias voltages, which reduces the gain of the first set (M₂) by increasing the bias voltage on the second set (M₁), thereby increasing M₁'s gain and shunting the alternating signal current away from M₂ (para [0005]). For Claim 8, Cui teaches a method for phase control in this circuit by executing these exact bias-voltage control steps to keep the output phase constant across gain switches (para [0007]-[0008]). For Claim 12, Cui teaches a beamforming circuit (phased array transceiver) comprising the variable gain amplifier, a phase shifter, and an antenna array (FIGS. 17-18, para [0033], [0058]). PNG media_image2.png 604 568 media_image2.png Greyscale Fig. 1 of Ibrahim: a schematic illustration of an antenna apparatus 100, e.g., a phased array system/apparatus. Regarding Claim 12, although Cui describes the phase shifter and the variable gain amplifier as discrete components connected in series (FIG. 18, para [0033]), Cui does not explicitly teach integrating the variable gain amplifier structurally within a unified "phase shifter module" that is directly coupled to the antenna array. Ibrahim, which is in the same field of endeavor (phased array transceivers and variable gain amplifiers), teaches a beamformer array (120) (FIG. 1) comprising transceivers coupled to an antenna array (110) (FIG. 1) (col. 7, lines 1-15). Ibrahim teaches that within these beamforming circuits, phase shifters (126, 130) (FIG. 1) and variable gain amplifiers (128, 132) (FIG. 1) function collectively as an integrated unit to control phase and amplitude for directional steering (col. 7, lines 34-40, col. 3, lines 6-15). Ibrahim establishes that variable gain amplifiers perform critical gain calibration directly tied to phase accuracy, thereby treating the gain-control mechanism as an integrated architectural component of phase control (col. 3, lines 29-35). It would have been obvious to a person having ordinary skill in the art (POSITA) to rationally modify the phased array transceiver of Cui by integrating its variable gain amplifier structurally into a unified phase shifter module as taught by Ibrahim. This modification results in a single-phase shifter module comprising the parallel transistor architecture to perform both amplitude adjustment and integrated phase control simultaneously. The motivation for this modification, as explicitly mentioned in Ibrahim, is to eliminate phase errors that arise due to process variations and mismatches during gain calibration (col. 3, lines 29-35). Integrating the bias-control mechanism into the phase shifter module ensures a substantially constant phase response across a wide range of gain values (col. 3, lines 29-35). This highly linear operation prevents deviations in the main beam direction and improves overall directional steering precision in the beamforming circuit (col. 3, lines 20-28). Claims 2-7 and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Cui in view of Ibrahim (US 11,277,108 B1), and further in view of Dykstra (US 2017/0133989 A1). Regarding Claims 2 and 10 (Bipolar Transistors), Cui teaches the fundamental architecture of the parallel sets of transistors within the programmable amplifier (FIG. 1, para [0005]). Cui illustrates the parallel sets of transistors specifically as MOSFETs and does not explicitly teach utilizing bipolar transistors (FIG. 1, para [0005]). Dykstra, in the same field of RF stacked/parallel amplifier configurations, teaches that the individual active transistor devices can be constructed using bipolar junction transistors (BJTs) (para [0120]). It would have been obvious to a person having ordinary skill in the art to modify the parallel transistor architecture of Cui/Ibrahim by substituting the MOSFETs with bipolar transistors, as taught by Dykstra. Dykstra explicitly mentions that substituting the components with bipolar transistors yields high-frequency voltage handling performance benefits depending on the specific semiconductor architecture and substrate implemented in the system (para [0120]). Rejection of Claim 3 (Complete Attenuation at Equal Bias), Cui teaches supplying parallel sets of transistors with independent, variable bias voltages to dictate the alternating current routing (FIG. 1, para [0005]). Cui, however, does not explicitly state that when the first and second bias voltages are perfectly equal, the output signal is "completely attenuated." Ibrahim teaches a cross-coupled variable gain switching arrangement where, when the differential bias control voltages reach a designated overlapping or equal state, it realizes a complete subtraction of currents, thereby applying the "minimum gain" (i.e., complete attenuation) to the output (FIGS. 2A-4B, col. 4, lines 15-26). It would have been obvious to a person having ordinary skill in the art to calibrate the bias control module of Cui to execute the current subtraction mechanism taught by Ibrahim when the first and second biases are equal. The motivation for this modification is to allow the programmable amplifier to achieve a highly isolated OFF state (zero-gain state) utilizing the existing parallel transistor framework, removing the need for separate, bulky discrete RF switches in the signal path (col. 4, lines 15-30). Regarding Claims 4 and 6 (Resistance Elements & Third Set of Transistors), Cui in view of Ibrahim Cui teaches the first and second parallel sets of transistors coupled to a third set of transistors (explicitly shown as common-source transistor M₃) (FIG. 1, para [0005]). Cui, however, does not explicitly detail the first and second sets of transistors being coupled to first and second resistance elements for biasing. Ibrahim teaches an active variable gain/programmable amplifier cross-coupled architecture wherein the parallel sets of transistors are coupled to a third transistor (M1) (FIG. 2A), and the signal paths are explicitly coupled to first and second resistance elements (resistors 230-1 and 230-2) (FIG. 2A, col. 4, lines 60-65). It would have been obvious to a person having ordinary skill in the art to incorporate the resistance elements of Ibrahim into the parallel transistor paths of Cui's programmable amplifier. The motivation for adding the resistance elements is to provide proper source degeneration and stabilize the current steering across the parallel sets of transistors, thereby improving the overall linearity of the vector synthesis phase control (col. 4, lines 26-30). Regarding of Claim 5 (Feedback Resistance Elements), Cui teaches the control module adjusting bias voltages across the parallel transistor networks (FIG. 1, para [0021]). Cui, however, does not explicitly teach the resistance elements acting as a feedback loop to adjust the output signal specifically due to capacitance variations. Dykstra teaches employing tunable resistance networks (e.g., an RC series network) (2110) (FIG. 20) to create an active feedback loop around the amplifier stage to optimize the amplifier's response and compensate for variations, including capacitance loads, when the mode or gain switches (para [0218]-[0219], [0236], [0265]). It would have been obvious to a person having ordinary skill in the art to configure the resistance elements of the Cui/Ibrahim amplifier to act as a feedback loop, as taught by Dykstra. The motivation for this modification, as stated by Dykstra, is to smooth the transition between gain states by compensating for abrupt capacitance load changes, thus removing glitches and ensuring a constant output signal phase during switching (para [0236]). Regarding Claims 7, 9, and 11 (Bidirectional Control & Beam steering), Cui teaches a programmable amplifier and method for phase control wherein a control module is adapted to reduce the gain of the second set of transistors while increasing the gain of the first set of transistors (bidirectional/inverse current steering) (FIG. 2(c), 2(d), para [0063]). Cui also teaches that this circuit is adapted for beam steering an antenna, explicitly disclosing a phased array transceiver used for beam receiving and sending in a fixed direction (FIG. 17, para [0034], [0058]). Cui, however, does not explicitly teach integrating this bidirectional programmable amplifier strictly within a unified "phase shifter module" directly coupled to the antenna. Ibrahim, in the same field of endeavor, teaches a unified beamformer architecture where the phase shifter (126, 130) (FIG. 1) and programmable amplifier (128, 132) (FIG. 1) act as an integrated phase shifter module coupled to an antenna array (110) (FIG. 1) to execute bidirectional phase and amplitude scaling (col. 7, lines 34-40). It would have been obvious to a person having ordinary skill in the art to modify the phased array transceiver of Cui by integrating the bidirectional programmable amplifier directly into a unified phase shifter module, as taught by Ibrahim. The motivation for this modification is to eliminate phase errors caused by process variations and mismatches, ensuring a highly linear, wideband operation for precision beam steering without signal deviation (col. 3, lines 20-35, col. 4, lines 26-30). Conclusion The prior art, Rossi (US 2002/0166948 A1) made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached on (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
Read full office action

Prosecution Timeline

Mar 22, 2024
Application Filed
Jul 02, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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3y 1m to grant Granted Jul 14, 2026
Patent 12683561
MULTI-OUTPUT SUPPLY GENERATOR WITH PARALLEL CONVERTERS
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
99%
With Interview (+8.4%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 734 resolved cases by this examiner. Grant probability derived from career allowance rate.

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