DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-13 are pending.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed: DISPLAY SUBSTRATE AND DISPLAY APPARATUS WITH COLUMNS OF SUB-PIXELS WITHIN A SAME CYCLE PERIOD ELECTRICALLY CONNECTED WITH DISCHARGE WIRES PROVIDING DIFFERENT DIRCT CURRENT SIGNALS.
Election / Restriction
Claim 6 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on Apr. 27, 2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8, 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Um et al. (US 2024/0185812 A1) in view of Long et al. (US 2021/0278731 A1).
As to claim 1, Um teaches a display substrate (Um, FIG. 1, [0024], a display substrate of the “display panel”), comprising:
a plurality of pixels (Um, FIGS. 1-2, [0024], “a pixel includes three sub-pixels 101”) arranged in an array (Um, see FIGS. 1-2), wherein each of the plurality of pixels (Um, FIGS. 1-2, [0024], “a pixel includes three sub-pixels 101”) comprises a plurality of sub-pixels (Um, FIG. 1, [0024], “three sub-pixels 101”; FIG. 2A, [0034], “a first sub-pixel 1011, a second sub-pixel 1012, and a third sub-pixel 1013”), each of the plurality of sub-pixels (Um, FIG. 1, [0024], “three sub-pixels 101”; FIG. 2A, [0034], “a first sub-pixel 1011, a second sub-pixel 1012, and a third sub-pixel 1013”) comprises a first domain area (Um, FIG. 2A, [0024], “main pixel electrode 1001”) and a second domain area (Um, FIG. 2A, [0024], “auxiliary pixel electrode 1002”);
a plurality of data lines (Um, FIGS. 1-2, [0029], “data line DL”), wherein each of the plurality of data lines (Um, FIGS. 1-2, [0028-0029], “data line DL”) is electrically connected with first domain areas (Um, FIGS. 1-2, [0028], “each of the data lines DL is electrically connected to the main pixel electrode 1001 through the first transistor T1”) and second domain areas (Um, FIGS. 1-2, [0029], “the main pixel electrode 1001 and the auxiliary pixel electrode 1002 of the same sub-pixel 101 are electrically connected to the same data line DL”) of a same column of sub-pixels (Um, see FIGS. 1-2); and
a plurality of discharge wires (Um, FIGS. 1-2, [0030], “sharing lines SHL1 SHL2 SHL3”), wherein each of the plurality of discharge wires (Um, FIGS. 1-2, [0030], “sharing lines SHL1 SHL2 SHL3”) is electrically connected with the second domain areas (Um, see FIG. 2B, [0030], “each of the sharing lines SHL is electrically connected to the auxiliary pixel electrode 1002”) of the same column of sub-pixels (Um, see FIGS 1-2), and the plurality of discharge wires (Um, FIGS. 1-2, [0030], “sharing lines SHL1 SHL2 SHL3”3) are configured to provide at least two direct current signals to two adjacent columns of pixels (Um, FIGS. 2-4, [0040], “a plurality of shared voltage signals may be direct current signals, as shown in FIG. 4A”).
Um does not teach “the first domain area and the second domain area each has at least two orientations”.
However, Long teaches the concept that the first domain area (Long, FIG. 5, [0038], “first sub-pixel region 30”) and the second domain area (Long, FIG. 5, [0038], “second sub-pixel region 40”) each has at least two orientations (Long, see FIG. 5, [0046], “an angle between extension directions of slits in any two adjacent slit groups 80 in the first slit electrode ranges from 10° to 170°, and an angle between extension directions of slits in any two adjacent slit groups 80 in the second slit electrode ranges from 10° to 170°”).
At the time of effective filing date, it would have been obvious to one of ordinary skill in the art to modify the “pixel electrodes 1001 1002” taught by Um to further comprise the “slit groups 80”, as taught by Long, in order to address the problem that “as a valid optical path difference is varying, there is also a varying proportion of transmittances of monochromatic light in red, green, and blue, so that there may be a color cast while the liquid crystal panel is being viewed at a side angle of view, thus degrading the display effect of the liquid crystal display” (Long, [0004]).
As to claim 8, Um teaches the display substrate according to claim 1, further comprising at least two terminals, wherein a same terminal is electrically connected with discharge wires providing a same direct current signal (Um, see FIG. 2B, [0031], “A terminal of the first storage capacitor Cst1 is connected in series between one of the source or the drain of the first transistor T1 and the second electrode layer Acom, one terminal of the second storage capacitor Cst2 is connected in series between one of the source or drain of the second transistor T2 and the second electrode layer Acom, the second electrode layer Acom may be located on the array substrate, and the second electrode layer Acom has a second common voltage”).
As to claim 11, Um in view of Long teaches the display substrate according to claim 1, further comprising a gate line (Um, FIG. 2A-2B, [0026], “scan lines SL”), wherein, the second domain area (Um, FIGS. 1-2A, [0029], “auxiliary pixel electrode 1002”) comprises a first transistor (Um, FIGS. 2A-2B, [0028], “transistor T2”) and a second transistor (Um, FIGS. 2A-2B, [0028], “transistor T3”), a gate of the first transistor (Um, FIGS. 2A-2B, [0028], “transistor T2”) is electrically connected with (Um, see FIG. 2B) the gate line (Um, FIG. 2A-2B, [0026], “scan lines SL”), a first electrode of the first transistor (Um, FIGS. 2A-2B, [0028], “transistor T2”) is electrically connected with (Um, see FIG. 2B) the data line (Um, FIG. 2B, [0029], “data line DL”), a second electrode of the first transistor (Um, FIGS. 2A-2B, [0028], “transistor T2”) is electrically connected with (Um, see FIG. 2B) a first electrode of the second transistor (Um, FIGS. 2A-2B, [0028], “transistor T3”), a gate of the second transistor (Um, FIGS. 2A-2B, [0028], “transistor T3”) is electrically connected with (Um, see FIG. 2B) the gate line (Um, FIG. 2A-2B, [0026], “scan lines SL”), and a second electrode of the second transistor (Um, FIGS. 2A-2B, [0028], “transistor T3”) is electrically connected with (Um, see FIG. 2B) the discharge wire (Um, FIGS. 2A-2B, [0030], “sharing line SHL”); and
ratios of channel width-to-length ratios of first transistors to channel width-to-length ratios of second transistors in adjacent pixels or adjacent sub-pixels in a row direction are different (Long, FIGS. 1-2, [0038], “design parameters of the two thin film transistors 50 can be changed to provide the two thin film transistors 50 with different channel width to length ratios so as to provide the first sub-pixel region 30 and the second sub-pixel region 40 with different voltage as needed”). Examiner renders the same motivation as in claim 1.
As to claim 13, Um teaches a display apparatus (Um, FIG. 1, [0020], the “display panel”), comprising the display substrate (Um, FIG. 1, [0024], the display substrate of the “display panel”) according to claim 1.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Um et al. (US 2024/0185812 A1) in view of Zhang (US 2022/0319457 A1).
As to claim 7, Um does not teach the display substrate according to claim 1, wherein the data lines provide data signals with two polarities for columns of sub-pixels in a same column of pixels.
However, Zhang teaches the concept that the data lines provide data signals with two polarities for columns of sub-pixels in a same column of pixels (Zhang, see FIG. 3, [0009], “two data lines are disposed between the sub-pixels of two adjacent columns, and the sub-pixels arranged in any one column correspond to two data lines with different polarities”).
At the time of effective filing date, it would have been obvious to one of ordinary skill in the art to modify the “data lines DL” taught by Um to further provide data signals with “two different polarities”, as taught by Zhang, in order to provide that “it is avoided that due to a fact that there are many sub-pixels of the same polarity arranged together during display, an area of the sub-pixels of the same polarity is too large, resulting in a graininess in a display image, thereby improving the display quality” (Zhang, [0029]).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Um et al. (US 2024/0185812 A1) in view of Wang (US 2017/0160604 A1).
As to claim 9, Um does not teach the display substrate according to claim 8, further comprising at least two filter circuits, wherein the filter circuits are connected between the at least two terminals and the discharge wires providing different direct current signals, respectively.
However, Wang teaches the concept of at least two filter circuits (Wang, see FIGS. 3 and 5, [0029], “filter capacitor”), wherein the filter circuits (Wang, see FIGS. 3 and 5, [0029], “filter capacitor”) are connected to the discharge wires (Wang, see FIG. 3, [0030], “metal wire 003”).
At the time of effective filing date, it would have been obvious to one of ordinary skill in the art to modify the “terminals” and the “sharing lines SHL” taught by Um to be further connected to the “filter capacitor” therebetween, as taught by Wang, in order to provide “a liquid crystal display panel and a display device for improving the Greenish effect of liquid crystal display panels” (Wang, [0006]).
As to claim 10, Um in view of Wang teaches the display substrate according to claim 9, wherein the filter circuit (Wang, see FIGS. 3 and 5, [0029], “filter capacitor”) comprises a resistor (Wang, FIG. 3, [0029], “resistance R”) and a capacitor (Wang, FIG. 3, [0029], “C is a size of the filter capacitor”), wherein the resistor (Wang, FIG. 3, [0029], “resistance R”) is connected between the terminal (Um, see FIG. 2B, [0031], “A terminal of the first storage capacitor Cst1 is connected in series between one of the source or the drain of the first transistor T1 and the second electrode layer Acom, one terminal of the second storage capacitor Cst2 is connected in series between one of the source or drain of the second transistor T2 and the second electrode layer Acom, the second electrode layer Acom may be located on the array substrate, and the second electrode layer Acom has a second common voltage”) and the discharge wire (Um, FIGS. 2A-2B, [0030], “sharing line SHL”), and the capacitor (Wang, FIG. 3, [0029], “C is a size of the filter capacitor”) is connected between the discharge wire (Um, FIGS. 2A-2B, [0030], “sharing line SHL”) and ground (Wang, see FIG. 3). Examiner renders the same motivation as in claim 9.
Allowable Subject Matter
Claims 2-5 and 12 would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 2, the closest known prior art, i.e., Um et al. (US 2024/0185812 A1), Long et al. (US 2021/0278731 A1), Zhang (US 2022/0319457 A1), Wang (US 2017/0160604 A1), Um (US 2018/0157080 A1), Wu et al. (US 2025/0231451 A1) and Huang (US 2022/0020337 A1), alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “wherein every at least two adjacent columns of sub-pixels are a cycle period, and the columns of sub-pixels within a same cycle period are electrically connected with discharge wires providing different direct current signals, respectively”.
As to claims 3-5, they depend from claim 2, and are allowable at least for the same reason above.
As to claim 12, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “wherein in the adjacent pixels or the adjacent sub-pixels in the row direction, the channel width-to-length ratios of the first transistors are same, and the channel width-to-length ratios of the second transistors are different”.
Conclusion
The prior arts made of record and not relied upon are considered pertinent to applicant’s disclosure:
Um (US 2018/0157080 A1) teaches the concept of “each of the first pixel array and the second pixel array having at least one domain tilting direction” (Abs.);
Wu et al. (US 2025/0231451 A1) teaches the concept that “a channel width and a channel length of a second driving thin film transistor and a channel width a channel length of a voltage division thin film transistor satisfy a preset equation” (Abs.); and
Huang (US 2022/0020337 A1) teaches the concept that “the first domain area and the second domain area each has at least two orientations” (e.g., FIGS. 1 and 4).
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD J HONG whose telephone number is (571) 270-7765. The examiner can normally be reached on 9:00 AM to 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on (571) 272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Sep. 14, 2026
/RICHARD J HONG/Primary Examiner, Art Unit 2623
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