DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: WIRELESS RADIO FREQUENCY RECEIVING DEVICE AND CONTROL METHOD TO SOLVE THE PROBLEMS OF UNSTABLE EFFECTIVE BANDWIDTH SIGNAL STRENGTH, LOW SIGNAL STRENGTH AND LARGE ERROR OF DIGITAL SIGNAL GAIN CONTROL ACCURACY
Claim Objections
Claim 1 is objected to because of the following informalities: lines 9-10 recite, “a gain controller connected between an output end of the detection chip.” It should be corrected to “the detection chips”, in order bto provide proper antecedence to “at least two detection chips” in line 8. Appropriate correction is required.
Claim 6, is objected to because of the following informalities: line 2 recites, “the detection chip is an amplitude detection chip and/or a power detection chip”. It should be corrected to “the detection chips”. Further, claim 6 recites: “the detection chip is an amplitude detection chip and/or a power detection chip”. While logically interpretable as covering three alternatives - amplitude only, power only, or both, the “and/or” construction is not the preferred form at the USPTO (see MPEP 2173.05(o)). Appropriate correction is required.
Claim 9 is objected to because of the following informalities: lines 7-8 recite, “the detection chip”. It should be corrected to “the detection chips”. Appropriate correction is required.
Claim 10 is objected to because of the following informalities: line 2 recites, “the detection chip”. It should be corrected to “the detection chips”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6, 8 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Coban (US 10469112, hereinafter “Coban”).
Regarding claim 1, Coban discloses,
A wireless radio frequency receiving device ( FIG. 1 is a block diagram of a receiver in accordance with an embodiment), comprising:
a signal transmission link (Fig. 1; attenuator 10 [Wingdings font/0xE0] LNA 20 [Wingdings font/0xE0] mixer 25 [Wingdings font/0xE0] TIA 30 [Wingdings font/0xE0] PGA 50 [Wingdings font/0xE0] ADC 60, i.e., series-connected receive chain) comprising a radio frequency front-end chip (Fig. 1; combination of LNA 20, mixer 25, TIA 30, LPF 40 and PGA 50) and a radio frequency transceiver chip (Fig. 1; combination of ADC 60 and DSP 70) which are connected in series (Fig. 2 shows all of these components are connected in series), wherein the radio frequency front-end chip is used for converting a received wireless signal into an analog electrical signal ( the RF signal is provided to a low noise amplifier (LNA) 20. After amplification in LNA 20, the RF signal is provided to a mixer 25. In various embodiments, mixer 25 may downconvert the RF signal to an IF signal. From there, the IF signal is provided to a transimpedance amplifier (TIA) 30, which converts mixer IF current into a voltage signal, Col. 4; lines 58-65) and amplifying (second gain control region 22 (and in some cases specifically LNA 20) may have a controllable gain that ranges from 4 dB to 30 dB, Col. 5; lines 1-3) and filtering the analog electrical signal (the output of TIA 30 is provided to a low pass filter (LPF) 40 for low pass filtering, Col 5; lines 15-17), and the radio frequency transceiver chip is used for converting the analog electrical signal into a digital electrical signal (Note that the IF signal output from PGA 50 is provided to a digitizer, namely an analog-to-digital converter (ADC) 60….. the digitized output of ADC 60 (Dout) is provided to a digital signal processor (DSP) 70, Col. 5; lines 24-45);
at least two detection chips (Fig. 1; a first peak detector 15 and second peak detector 55) respectively connected to the signal transmission link (Fig. 1 shows the first peak detector 15 and second peak detector 55 are connected at different points of the receive chain), wherein the detection chips are used for detecting a signal parameter in the series link (The RF signal after attenuation in attenuator 10 is further provided to a first peak detector 15, which operates as a wide-band detector to compare the power of the RF signal output from attenuator 10 to a first threshold (Pth1). When the RF signal level exceeds this threshold, peak detector 15 outputs an active detection signal, RFpkd, to an AGC controller 80, Col. 5; lines 4-10…this IF signal is further provided to another peak detector 55, which in the embodiment shown is an IF peak detector. Peak detector 55 operates as a narrowband detector to compare this IF signal power to a second threshold (Pth2), Col. 5; lines 24-30); and
a gain controller (Fig. 1; AGC controller 80) connected between an output end of the detection chip (Fig. 1 shows AGC controller 80 directly receives detection signal RFpkd 15 and IFpkd 55, i.e., it is connected to the output ends of both detection chips) and the radio frequency front-end chip (Fig. 1 shows output RSSI from DSP 70 is provided to AGC controller), wherein the gain controller is used for adjusting a gain coefficient of the radio frequency front-end chip according to the signal parameter (the AGC techniques described herein may first perform gain control of the gain components using signal information obtained from power detectors (also referred to herein as peak detectors) within radio frequency (RF) and intermediate frequency (IF) sections of the receiver. Then, only optionally may received signal strength indicator (RSSI) information that is obtained from digitally processed signal information be used to (potentially) fine tune one or more of the gain components, Col. 4; lines 1-5).
Regarding claim 2, Coban discloses,
wherein the at least two detection chips have different connection points with the signal transmission link (Fig. 1 shows the first peak detector 15 and second peak detector 55 are connected at different points of the receive chain).
Regarding claim 3, Coban discloses,
wherein the signal transmission link comprises a digital filter chip connected with the radio frequency transceiver chip, and the digital filter chip is used for filtering the digital electrical signal (the digitized output of ADC 60 (Dout) is provided to a digital signal processor (DSP) 70. As illustrated, channel filtering may be performed in a channel filter 75. Furthermore, DSP 70 may analyze the channel filtered output to determine RSSI information which may be used to perform fine tuning of one or more of the gain components, Col. 5; lines 42-46).
Regarding claim 6, Coban discloses,
wherein the detection chip is an amplitude detection chip and/or a power detection chip ((Fig. 1; a first peak detector 15 and second peak detector 55).
Regarding claim 8, Coban discloses,
an antenna (antenna 3; Fig. 1) connected with the radio frequency front-end chip and used for receiving the wireless signal (an integrated circuit (IC) including the receiver, receives an incoming RF signal (RFin) from an antenna 3, Col. 3; lines 39-44); and
a baseband chip (Fig. 1 shows DSP 70 receiving the digitized output Dout from ADC 6. DSP is the terminal processing block of the receiver chain, which process downcoverted RF signal , Col. 5; lines 42-49), wherein
when the wireless radio frequency receiving device comprises a digital filter chip but does not comprise the digital gain control chip, the baseband chip is connected with the digital filter chip (the digitized output of ADC 60 (Dout) is provided to a digital signal processor (DSP) 70. As illustrated, channel filtering may be performed in a channel filter 75. Furthermore, DSP 70 may analyze the channel filtered output to determine RSSI information which, as described herein, may be used to perform fine tuning of one or more of the gain components, in certain cases. DSP 70 may also digitally process and output processed data, Col. 5; lines 42-49); or
the baseband chip is used for format and interface conversion of a filtered digital signal (the digitized output of ADC 60 (Dout) is provided to a digital signal processor (DSP) 70. As illustrated, channel filtering may be performed in a channel filter 75. Furthermore, DSP 70 may analyze the channel filtered output to determine RSSI information which, as described herein, may be used to perform fine tuning of one or more of the gain components, in certain cases. DSP 70 may also digitally process and output processed data, Col. 5; lines 42-49).
Regarding claim 10, Coban discloses,
controlling the detection chip to obtain a signal parameter in the signal transmission link (The RF signal after attenuation in attenuator 10 is further provided to a first peak detector 15, which operates as a wide-band detector to compare the power of the RF signal output from attenuator 10 to a first threshold (Pth1). When the RF signal level exceeds this threshold, peak detector 15 outputs an active detection signal, RFpkd, to an AGC controller 80, Col. 5; lines 4-13…. Peak detector 55 operates as a narrowband detector to compare this IF signal power to a second threshold (Pth2). In one embodiment, this second threshold Pth2 may be set at −15 dBm, although of course other values are possible. As with the discussion above, when the IF signal level exceeds this threshold, peak detector 55 outputs an active detection signal, IFpkd, to AGC controller 80, Col. 5; lines 24-35);
controlling the gain controller to generate a gain adjustment signal according to the signal parameter and a signal target threshold (Peak detector 55 operates as a narrowband detector to compare this IF signal power to a second threshold (Pth2). In one embodiment, this second threshold Pth2 may be set at −15 dBm, although of course other values are possible. As with the discussion above, when the IF signal level exceeds this threshold, peak detector 55 outputs an active detection signal, IFpkd, to AGC controller 80, Col. 8; lines 50-Col. 9; lines 25); and
controlling the radio frequency front-end chip to adjust a gain coefficient according to the gain adjustment signal, so that a strength difference between a strength of a signal output by the wireless radio frequency receiving device and a target strength is within a preset range (an AGC technique may be adapted to settle at the arrival of a packet before an actual payload starts. At the end of the process, gain is typically settled to a minimum level at which a required signal-to-noise ratio (SNR) (such as a SNR specified by a receiver manufacturer, or a SNR specified by a given communication protocol) is met with a few decibels (dB) of margin. In this way, the dynamic range of the receive chain is maximized and therefore the saturation of a receiver channel is prevented if a relatively strong blocker arrives during reception of desired data, Col. 4; lines 11-26).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Coban, and further in view of Takatz et al. (US 7483500, hereinafter “Takatz”).
Regrading claim 4, Coban discloses everything claimed as applied above (see claim 3), further Coban discloses, wherein an input end of at least one of the detection chips is electrically connected between the radio frequency front-end chip (Fig. 1 shows the input of IFPkd 55 is in between RF front-end chip (i.e, combination of LNA 20, mixer 25, TIA 30, LPF 40 and PGA 50) and the radio frequency transceiver chip (Fig. 1; combination of ADC 60 and DSP 70)) and an input end of at least one of the detection chips is electrically connected to an output end of the digital filter chip (Fig. 1 shows output RSSI from DSP 70 is provided to AGC controller).
However, Coban does not disclose, an input end of at least one of the detection chips is electrically connected between the radio frequency transceiver chip and the digital filter chip.
In the same field of endeavor, Takatz discloses, an input end of at least one of the detection chips (i.e., input of wide-band variance 22) is electrically connected between the radio frequency transceiver chip (ADC 14; Fig. 1) and the digital filter chip (digital filter 15; Fig 1) (Fig. 1 shows an input of detector chip (i.e., combination of block 22 and block 23) is in between ADC 14 and filter 15) .
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Coban by specifically providing an input end of at least one of the detection chips is electrically connected between the radio frequency transceiver chip and the digital filter chip, as taught by Takatz for the purpose of reducing complexity by using a fixed set of filter coefficients and switching control of the AGC loop from narrowband to wideband power calculations as necessary (Col. 2; lines 20-25).
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Coban, and further in view of Murthy et al. (US 8605836, hereinafter “Murthy”).
Regarding claim 5, Coban discloses everything claimed as applied above (see claim 1). However, Murthy does not disclose, a digital gain control chip, wherein an input end of the digital gain control chip is connected with an output end of the digital filter chip; at least one of the detection chips is connected with an output end of the digital gain control chip; and an output end of the gain controller is connected with the digital gain control chip.
In the same field of endeavor, Murthy discloses, a digital gain control chip (i.e., DVGA 230; Fig. 2), wherein an input end of the digital gain control chip is connected with an output end of the digital filter chip (Within AGC unit 170, a DC offset removal unit 222 estimates and removes direct current (DC) offset in the input samples. A DVGA 230 multiplies the samples from unit 222 with a variable digital gain GD and provides output samples x(k) having the desired average power, Col. 6; lines 48-55); at least one of the detection chips (i.e., power detector 240; Fig. 2) is connected with an output end of the digital gain control chip (Fig. 2 shows output of DVGA 230 is connected to power detector 240); and an output end of the gain controller is connected with the digital gain control chip (Fig. 2 shows output of AGC controller 250 is connected to DVGA 230 via digital gain computation 260).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Coban by specifically providing a digital gain control chip, wherein an input end of the digital gain control chip is connected with an output end of the digital filter chip; at least one of the detection chips is connected with an output end of the digital gain control chip; and an output end of the gain controller is connected with the digital gain control chip, as taught by Murthy for the purpose of performing AGC at a wireless receiver in an efficient and cost-effective manner (Col. 1; lines 43-45).
Regarding claim 7, the combination of Coban and Murthy discloses everything claimed as applied above (see claim 5), in addition Murthy discloses, wherein a gain coefficient corresponding to the digital gain control chip is less than a gain coefficient corresponding to the radio frequency front-end chip (AGC controller 250 provides to a digital gain computation unit 260 a control signal d(n) that is indicative of the average power of the baseband signal, after taking into account the analog gain G.sub.A to be applied to receiver unit 160. Unit 260 selects a suitable digital gain G.sub.D for DVGA 230 such that the average power of the output samples is maintained at or near the DVGA setpoint, Col 6; lines 60-Col. 7; lines 6).
Allowable Subject Matter
Claims 9 and 11-15 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding claim 9, The following is a statement of reasons for the indication of allowable subject matter: the closest prior art, Coban, does not teach nor fairly suggest the following novel feature:
“the wireless radio frequency receiving device comprising a baseband chip, wherein an input end of the baseband chip is connected with an output end of the radio frequency transceiver chip, and the baseband chip is used for format and interface conversion of a filtered digital signal; and a field programmable gate array comprising a gain correlation interface, a digital signal interface and a signal parameter reading interface, wherein the gain correlation interface is connected with the radio frequency front-end chip, the digital signal interface is connected with an output end of the baseband chip, the signal parameter reading interface is connected with the detection chip, the field programmable gate array is used for filtering the digital electrical signal, and the field programmable gate array is further used for adjusting a gain coefficient of the radio frequency front-end chip according to a signal parameter before digital filtering processing and a signal parameter after digital filtering processing”, in combination with the other limitations in claim 1.
Regarding claim 11, The following is a statement of reasons for the indication of allowable subject matter: the closest prior art, Coban, does not teach nor fairly suggest the following novel feature:
“wherein when the wireless radio frequency receiving device comprises a digital filter chip, the method further comprises: controlling the at least two detection chips to respectively obtain signal parameters corresponding to different positions of the signal transmission link connected therewith, wherein the signal parameters comprise a first signal parameter, a second signal parameter and a third signal parameter, the first signal parameter is a signal parameter between the radio frequency front-end chip and the radio frequency transceiver chip, the second signal parameter is a signal parameter between the radio frequency transceiver chip and the digital filter chip, and the third signal parameter is a signal parameter output by an output end of the digital filter chip; generating a plurality of gain adjustment signals according to different signal parameters and different target thresholds, wherein the gain adjustment signals comprise a first gain adjustment signal, a second gain adjustment signal and a third gain adjustment signal, the first gain adjustment signal corresponds to the first signal parameter, the second gain adjustment signal corresponds to the second signal parameter, and the third gain adjustment signal corresponds to the third signal parameter; and controlling the radio frequency front-end chip to adjust the gain coefficient according to at least one of the first gain adjustment signal, the second gain adjustment signal and the third gain adjustment signal, so that the strength difference between the strength of the signal output by the wireless radio frequency receiving device and the target strength is within the preset range”, in combination with the other limitations in claim 1 and claim 10.
Claims 12-14 are allowed as those inherit the allowable subject matter from claim 11.
Regarding claim 15, The following is a statement of reasons for the indication of allowable subject matter: the closest prior art, Coban, does not teach nor fairly suggest the following novel feature:
“wherein when the wireless radio frequency receiving device comprises a field programmable gate array, the method further comprises: controlling the field programmable gate array to filter the digital electrical signal; and controlling the field programmable gate array to adjust a gain coefficient of the radio frequency front-end chip according to a signal parameter before digital filtering processing and a signal parameter after digital filtering processing”, in combination with the other limitations in claim 1 and claim 10.
Prior Art of the Record:
The prior art made of record not relied upon and considered pertinent to
Applicant’s disclosure:
EP 20890021: Embodiments of the present disclosure provide a radio frequency receiving link and a radio frequency transceiving device, which can at least solve the problem in the related art that efficient frequency calibration cannot be implemented for a receiving link in a radio frequency transceiver.
US 20160182108: The apparatus has a frequency component detecting circuit which samples intermediate frequency signal using over-sampling frequency that is variable and detects frequency components in intermediate frequency signal.
US 9288776: Aspects of the present disclosure relate generally to wireless communication systems, and more particularly, to a wideband receiver with automatic gain control for supporting multiple carriers with possibly different air interface technologies in a single wideband receiver chain.
Conclusion
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/GOLAM SOROWAR/Primary Examiner, Art Unit 2641