DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
3. Claim 13 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ngo et al. (US Publication Number 2018/0217959, hereinafter “Ngo”).
4. As per claim 13, Ngo teaches a slave circuit (slave IC 14, figure 1, paragraph 4) in a single-wire bus circuit (bus interface system 10, figure 1, paragraph 3), the slave circuit is coupled to a master circuit (master IC 12, figure 1, paragraph 3) via a single-wire bus (bus line 16, figure 1, paragraph 3) and comprises (slave IC 14 receives data signal from master IC 12 over bus line 16, the one line carrying both the data and the charge, the stated object being to supply power over a single bus line as well as communication, figure 1, paragraphs 1 and 3): a power harvesting circuit (supply capacitor 56 at slave supply port P1, figure 1, paragraph 4) coupled to the single-wire bus (bus line 16, figure 1, paragraph 3) via a power switch (third PFET 50, figure 1, paragraph 4, supply capacitor 56 sits between slave supply port P1 and ground and stores power from the signal on bus line 16 to provide the slave supply voltage VDD, while a source and a drain of third PFET 50 are coupled to bus line 16 and to port P1 respectively, so the switch stands between the bus and the harvesting capacitor, figure 1, paragraph 4); and a slave control circuit (digital control circuit 48, figure 1, paragraph 4) configured to (digital control circuit 48 generates control signal CS from the edge detection signal EDS and the current detection signal CDS and applies it to the gate of third PFET 50, so it is the circuit that opens and closes the switch, figure 1, paragraph 4): close the power switch during a fast-charge period wherein a bus voltage of the single-wire bus is held at a higher bus voltage level (master power supply VIO applied through second PFET 42 of switch circuit 20 turns on second PFET 42 after the rising edge so that a low impedance path of 0.2 to 0.5 ohms is formed from VIO to bus line 16) such that the power harvesting circuit can draw a bus current over the single-wire bus to thereby harvest power (edge detection circuit 46 activates FRO 58 at threshold of about half of VIO on the rising edge and digital control circuit 48 turns third PFET 50 on, the low RC charging time constant formed by it ON channel resistance and supply capacitor 56 allows the capacitor to recover significant charge from bus line 16 on almost any interval in which the bus is in a high state, and it remains connected through third PFET 50 as long as the bus stays high, figures 1, 2D, paragraph 5); and open the power switch to stop drawing the bus current (digital control circuit 48 drives the gate of third PFET 50 high, and the turned off transistor releases supply capacitor 56 from bus line 16 to avoid losing excessive charge, after which the bus voltage ramps down, figures 1 and 2d, paragraph 5) in response to detecting that the single-wire bus is pulled down to the lower bus voltage level (trigger 86 of aux standby circuit 84, figure 5, paragraph 6, reverse current detection circuit 54, figure 1, paragraph 4, two disclosed detections, figure 5 once the voltage level on bus line 16 drops to less than 0.8 to 0.9 times VDD the 86 output goes low and fourth PFET 98 is turned off which is a detection of the bus voltage itself falling in figure 1, master IC 12 pulls current from bus line 16 to ground through first NFET 28 to drive the bus low and the resulting voltage across third PFET 50 is detected by reverse current detection circuit 54, which causes switched to be turned off, paragraphs 5 and 6).
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Ngo et al. (US Publication Number 2022/0166644, hereinafter “Ngo”) in view Visser et al. (US Publication Number 2008/0084945, hereinafter “Visser”).
7. As per claim 1, Ngo teaches a master circuit in a single-wire bus circuit, method, and device coupled to a plurality of slave circuits (plurality of slaves, 66/68, figure 2, paragraph 47) via a single-wire bus (62, figure 2, paragraph 47).
Ngo does not appear to explicitly disclose configured to apply a first drive strength during a first one of a plurality of clock cycles to thereby pull a bus voltage of the single-wire bus from a higher bus voltage level down to a first intermediate bus voltage level; apply a second drive strength higher than the first drive strength during a second one of the plurality of clock cycles immediately succeeding the first one of the plurality of clock cycles to thereby further pull the bus voltage of the single-wire bus from the first intermediate bus voltage level to a second intermediate bus voltage level; apply a third drive strength higher than the second drive strength during a third one of the plurality of clock cycles immediately succeeding the second one of the plurality of clock cycles to thereby further pull the bus voltage of the single-wire bus from the second intermediate bus voltage level to a third intermediate bus voltage level; and apply a fourth drive strength higher than the third drive strength during a fourth one of the plurality of clock cycles immediately succeeding the third one of the plurality of clock cycles to thereby further pull the bus voltage of the single-wire bus from the third intermediate bus voltage level to the lower bus voltage level.
However, Visser discloses configured to apply a first drive strength (one activated current source circuit 112 in series with its switch 124, figure 1, paragraph 16) during a first one of a plurality of clock cycles (clock circuit 121 feeding up/down Johnson counter 23 through clock enable 24, figures 1 and 3, paragraphs 16 and 24) to thereby pull a bus voltage of the single-wire bus from a higher bus voltage level (potential of second power supply connection V2 reached through pull down resistor 16, figures 1 and 2, paragraphs 16 and 17) down to a first intermediate bus voltage level (on the first transition driver 12 starts pulling potential B of bus conductor 14 away from V2 toward V1 control circuit 120 switching switches 124 on one after the other so progressively increases number of the current source circuits 122 supplies current to the conductor, paragraphs 17 and 18); apply a second drive strength higher than the first drive strength (all current source circuits 122 are designed to deliver substantially the same current so each added branch raises the drive strength above the preceding step and gives a substantially linear increase of driving strength as a function of time, paragraph 32) during a second one of the plurality of clock cycles immediately succeeding the first one of the plurality of clock cycles (counter 23 is a Johnson counter, which raises signal at increasing number of outputs as more clock pulses are received so the second step falls on the clock cycle immediately after the first with no cycle skipped, paragraphs 24 and 27) to thereby further pull the bus voltage of the single-wire bus from the first intermediate bus voltage level to a second intermediate bus voltage level (with second branch added, potential B continues away from V2 toward V1 and reaches a lower value than after the first step, paragraphs 17 and 18); apply a third drive strength higher than the second drive strength during a third one of the plurality of clock cycles immediately succeeding the second one of the plurality of clock cycles (the same counter mechanism continues one further switch per clock pulse and this summary covers both the drive-strength step and its clock cycle because it reaches both, paragraphs 18 and 27) to thereby further pull the bus voltage of the single-wire bus from the second intermediate bus voltage level to a third intermediate bus voltage level (three driver branches are shown in figure 1 and the reference states that a larger number may be present so the third step is within, paragraph 16); and apply a fourth drive strength higher than the third drive strength during a fourth one of the plurality of clock cycles immediately succeeding the third one of the plurality of clock cycles (counter adds one further branch per clock pulse until the level detector fires so a fourth cycle follows the third on the same mechanism, paragraphs 16 and 27) to thereby further pull the bus voltage of the single-wire bus from the third intermediate bus voltage level to the lower bus voltage level (potential on first power supply connection V1, figures 1 and 2, paragraphs 16 and 18, level detector 126 detects that potential B has reached the required range, whose top is indicated by top level 34 and control circuit 120 then switches on all switches 124 so that the conductor is pulled towards V1 with max strength, paragraphs 17 and 18).
Ngo and Visser are analogous art because they are from the same field of endeavor of device voltage transition management.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ngo and Visser before him or her, to modify the voltage handling of Ngo to include the voltage swings of Visser because to better fine tune the voltage.
One of ordinary skill would be motivated to make such modification in order to enhance voltage handling for the system, paragraphs 3 and 4 Therefore, it would have been obvious to combine Visser with Ngo to obtain the invention as specified in the instant claims.
8. Ngo modified by the teachings of Visser as seen in claim 1 above, as per claim 5, Ngo teaches a single-wire bus circuit and device , wherein the master circuit is further configured to progressively increase the drive strength by progressively reducing a pulldown resistance of the master circuit (paragraphs 58 – 60, adjusting resistor with respect to slave/master).
Allowable Subject Matter
9. Claims 9, 11, and 12 allowed.
Claims are 3, 4, 6 – 8, 14 – 17, 19, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
10. Applicant’s arguments with respect to claims have been considered but are moot because the new ground of rejection in light of Visser does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Examiner notes when adding allowable subject matter from dependent claims into independent claims to seek allowability the original claim elements should be maintained in the independent claim with all intervening elements. Claims 1 and 13 do not reflect maintenance of the intervening elements and therefor a new rejection is presented in light of the newly presented claims.
Conclusion
11. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ngo-601 teaches consecutive clock cycle drive strength adjustment.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AURANGZEB HASSAN whose telephone number is (571)272-8625. The examiner can normally be reached 7 AM to 3 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached at 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
AH
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
Prosecution Insights