DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on 06/23/24 has been considered by the examiner.
Priority
3. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
4. The disclosure is objected to because of the following informalities: on line 3 of the abstract of the disclosure, the word "includes" should be changed to --include--. On line 3 of paragraph [0003], the word "circuitry" is misspelled. On line 4 of paragraph [0004], the word --be-- should be inserted before "generated". On line 9 of paragraph [0006], the word "includes" should be changed to --include--, and note that the same change should also be made on line 12 of this paragraph. On the first line of paragraph [0021], the word "embodiment" should be changed to --embodiments--. On the second line of paragraph [0027], the word "indicates" (both occurrences) should be changed to
--indicate--. On line 4 of paragraph [0035], the word "generated" should be changed to
--output--. On line 3 of paragraph [0045], the word "input" should be changed to
--output--. On the second line of paragraph [0049], the word "the" should be deleted. On the second line of paragraph [0055], the word --the-- should be inserted before "ability". On the penultimate line of paragraph [0059], --3-- should be inserted before "is". On the penultimate line of paragraph [0062], a comma should be inserted after the word "disclosure". On the first line of paragraph [0102], the word "can" should be changed to
--will--. On the second line of paragraph [0111], the second occurrence of the word "is" should be changed to --are--. On the first line of paragraph [0115], the word "can" should again be changed to --will--. On the second line of paragraph [0132], the second occurrence of the word "is" should again be changed to --are--. On the first line of paragraph [0135], the word "can" should again be changed to --will--. On lines 1 and 3 of paragraph [0138], the word "to" (both occurrences) should be changed to --with--, i.e., circuit components are connected in series with or in parallel with each other, not in series to or parallel to each other. On line 5 of paragraph [0142], the word "connects" should be changed to --connect--. On line 4 of paragraph [0143], the word "can" should be changed to --will--. On the penultimate line of paragraph [0148], "A" should be changed to -- The--. On lines 1 and 2 of paragraph [0154], the word "is" (both occurrences) should be changed to --are--. On line 8 of paragraph [0197], the word "includes" should be changed to --include--. On line 5 of paragraph [0224], the word "The" should be changed to --the--.
Appropriate correction is required.
Claim Objections
5. Claims 1, 3, 5, 6, 8, 10, 13 and 17 are objected to because of the following informalities:
On line 4 of claim 1, the word "includes" should be changed to --include--.
On line 3 of claim 3, --a periphery of-- should be inserted after the word "and".
On the second line of claim 5, the word "at" should be changed to either
--during-- or --upon--, and note that the same change should also be made on lines 3-5 of this claim, for each occurrence of the word "at".
On line 3 of claim 6, the word "is" should be changed to --are--.
On the second line of claim 8, the word "comprises" should be changed to
--comprise--, and note that the same change should also be made on the second line of claim 10.
On the first line of claim 13, the word "comprises" should be changed to
--includes-- (note what is indicated on line 7 of claim 11).
On line 10 of claim 17, the word "includes" should be changed to --include--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112(b)
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 14 and 17-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
On lines 2-3 of claim 14, the recitation of "a plurality of capacitors" lacks clear antecedent basis, the reason being that claim 11 already recites first through third capacitors, note what is indicated on lines 8-10 thereof, i.e., it cannot be determined by the examiner if the recitation of a plurality of capacitors recited in claim 14 is referring to the same capacitors as the three capacitors recited on lines 8-10 of claim 11. Applicant should make appropriate amendments to claim 11 and/or claim 14 in order to clear up this ambiguity.
On line 13 of claim 17, "the supply modulator" lacks antecedent basis.
Claims 18-20 are rejected as being indefinite in view of their dependencies on indefinite claim 17.
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 5-11 and 13-18 are rejected under 35 U.S.C. 103 as being unpatentable over Perreault et al (USP 9,755,672) in view of Jin et al (USPAP 2022/0131469).
As to claim 1, Perreault et al discloses, in figures 7 and 8,
tracker module comprising:
a module laminate (although Perreault et al does not disclose a module laminate, such would have been obvious to one of ordinary skill in the art, the reason being that it was old and well-known in the art before the effective filing date of applicant's invention that a circuit such as that disclosed by Perreault et al is typically formed on a module laminate, of which fact official notice is taken by the examiner);
an integrated circuit (Perreault et al's integrated circuit which includes the switches shown in figure 8 and the inherent or obvious switches within output switching stage 16"in figure 7) disposed on the module laminate; and
a plurality of capacitors (the capacitors shown in figure 8 of Perreault et al) that are disposed on the module laminate and that include one or more capacitors in a switched-capacitor circuit that is configured to generate a plurality of discrete voltages (voltages V1 through VN) based on an input voltage (input voltage VIN);
wherein the integrated circuit includes a switch that is included in the
switched-capacitor circuit and a switch that is included in a supply modulator (supply modulator 16" inherently or obviously includes a plurality of switches) that is configured to selectively output at least one of the plurality of discrete voltages generated by the switched-capacitor circuit (the inherent function of output switching stage 16"is to selectively output at least one of the plurality of discrete voltages V1 through VN) generated by the switched-capacitor circuit;
wherein the plurality of capacitors include:
a first flying capacitor (any one of the three flying capacitors whose charging/discharging is controlled by the left-hand column of switches shown in figure 8 of Perreault et al) and a second flying capacitor (any one of the three flying capacitors whose charging/discharging is controlled by the right-hand column of switches shown in figure 8 of Perreault et al) that are configured to be charged and discharged in a complementary manner by repeating a first phase and a second phase (the claimed first phase and second phase read on phases PWM1 and PWM2, respectively, in Perreault et al) between the first line capacitor and the second flying capacitor,
a third flying capacitor (any additional one of the above-noted three flying capacitors whose charging/discharging is controlled by the left-hand column of switches shown in figure 8 of Perreault et al) that is configured to be charged at a same timing as the first flying capacitor and to be discharged at a same timing as the first flying capacitor (note that the three above-noted flying capacitors whose charging/discharging is controlled by the left-hand column of switches shown in figure 8 of Perreault et al are all charged and discharged at the same timing).
Not disclosed by Perreault et al is the limitation recited on the last two lines of claim 1, the second flying capacitor being disposed between the first and third flying capacitors. Such would have been obvious, however, to one of ordinary skill in the art in view of Jin et al, note figures 1A and 1B of this reference which disclose coupling a second capacitor (capacitor C3) between first and third capacitors (capacitor C1 and capacitor C2, respectively), where the first and third capacitors C1, C2 are charged/discharged at the same first timing and the second capacitor C3 is charged at a second timing which is complementary to the first timing. A person having ordinary skill in the art would have easily recognized that the above-noted second flying capacitor in figure 8 of Perreault et al should be disposed between the above-noted first and third flying capacitors in order to obtain the benefit taught by Jin et al, i.e., obtaining the AC ripple cancellation effect described in paragraph [0039] of this reference.
As to claim 2, note that Perreault et al's supply modulator 16" inherently is configured to control the output voltage applied to Filter Stage based on an envelope signal of the input signal VIN (inherently signal VIN has an envelope), and note that the recitation of a radio frequency signal is just a statement of intended use, i.e., input signal VIN is clearly capable of being an RF input signal.
As to claim 5, the recitation of a potential difference between a potential of the first and second flying capacitors during charging is a smallest potential difference of potential differences between the potential of the second flying capacitor during charging and potentials of flying capacitors other than the second flying capacitor during charging, although not disclosed by either Perreault et al or Jin et al, nevertheless would have been obvious to one of ordinary skill in the art, the reason being that it has long been held that discovering an optimum value of a result effective variable involves only routine skill in the art, see In re Boesch, 617 F.2d 272, 205, 205 USPQ 215 (CCPA 1980). The same is true for the limitation in claim 6 regarding the first line capacitor receiving a highest potential among potentials applied to the plurality of capacitors in the switched-capacitor circuit.
As to claim 7, the above-noted first through third flying capacitors will be either inherently or obviously adjacent to the above-noted integrated circuit, i.e., such will be the case by necessity because Perreault et al's capacitors shown in figure 8 are charged and discharged by the switches within the integrated circuit.
As to claim 8, the claimed filter circuit reads on Filter Stage shown in figure 7 of Perreault et al, note that this filter circuit includes three capacitors which are included in the one or more capacitors recited in claim 1, note that the filter circuit will inherently or obviously be positioned adjacent to the above-noted integrated circuit, and note that the filter circuit inherently is configured to filter signals output from Perreault et al's supply modulator 16".
As to claim 9, the above-noted filter circuit shown in figure 7 of Perreault et al is shown as including both an inductor and a resistor.
As to claim 10, the claimed pre-regulator circuit reads on magnetic regulation stage 12" shown in figure 7 of Perreault et al, note that such a magnetic regulation stage will inherently or obviously comprise one or more capacitors, and it will inherently or obviously be positioned adjacent to the above-noted integrated circuit, as illustrated in figure 7 of Perreault et al, and note that its function is to convert a voltage from a power source to the input voltage VIN.
As to claims 11 and 13, the limitations of these two claims are rejected using the same analysis as set forth above in the rejection of claims 1, 2 and 5-10 (note that this claim reads on the details of the switched-capacitor circuit 20 shown in applicant's figure 3, and note that Perreault et al's figure 8 switched-capacitor circuit has the same structure as applicant's switched-capacitor circuit 20, and therefore the first through fourth capacitors and the first through tenth switches recited in claim 11 will be anticipated by what is shown in Perreault et al's figure 8).
As to claims 14 and 15, the limitations of these two claims are rejected using the same analysis as set forth above with regard to claims 5 and 6.
As to claim 16, the claimed third circuit again reads on magnetic regulation stage 12" shown in figure 7 of Perreault et al.
As to claims 17 and 18, the limitations of these two claims are rejected using the same analysis as set forth above with regard to claims 1, 2 and 5-10 (the claimed signal processing circuit and power amplifier circuit are either inherent or obvious in Perreault et al, i.e., any person having ordinary skill in the art would have easily recognized that the output of the filter stage shown in figure 7 of this reference is obviously for application to the power supply input of a power amplifier circuit, and the circuitry disclosed by Perreault et al typically comprises the signal processor configured to process an RF input signal).
Allowable Subject Matter
8. Claims 3, 4 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 19 and 20 would be allowable if rewritten to overcome the rejection set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the prior art of record discloses or suggests the tracker module of claim 1 with the further limitation that, in a plan view of the module laminate, a periphery of the first line capacitor and the periphery of the third flying capacitor each have a rectangular shape and that the long edge of the first line capacitor intersects the long edge of the third flying capacitor, as recited in claim 3; nor does any of the prior art of record disclose or suggest the tracker module of claim 1 with the further limitation that the plurality of capacitors further include a smoothing capacitor which is disposed between the first and third flying capacitors, as recited in claim 4; nor does any of the prior art of record disclose or suggest the tracker module of claim 11 with the further limitation that, in a plan view of the module laminate, a periphery of the first line capacitor and the periphery of the third flying capacitor each have a rectangular shape and that the long edge of the first line capacitor intersects the long edge of the third flying capacitor, as recited in claim 12; nor does any of the prior art of record disclose or suggest the communication device of claim 17 with the further limitation that, in a plan view of the module laminate, a periphery of the first line capacitor and the periphery of the third flying capacitor each have a rectangular shape and that the long edge of the first line capacitor intersects the long edge of the third flying capacitor, as recited in claim 19; nor does any of the prior art of record disclose or suggest communication device of claim 17 with the further limitation that the plurality of capacitors further include a smoothing capacitor which is disposed between the first and third flying capacitors, as recited in claim 20.
Prior Art Not Relied Upon
9. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Liu et al (USP 12,028,980) discloses another example of a switched-capacitor circuit including a plurality of flying capacitors which are disposed on a substrate, which could obviously be a module laminate, together with a plurality of switches for controlling the charging and discharging of the flying capacitors.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH B WELLS whose telephone number is (571)272-1757. The examiner can normally be reached Monday-Friday, 8:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, REGIS J BETSCH, can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH B WELLS/Primary Examiner, Art Unit 2836 May 29, 2026
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