DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Exemplary claim 1 recites the following limitation: “the at least two persistent memories do not require an input/output (IO) interface operation”. Relevant supports are found in the specification:
[0007]It should be noted that the persistent memory is also referred to as a non-volatile memory (NVM), is configured to perform persistent storage on the data, and is a storage medium (also referred to as a memory or storage hardware) that does not lose the data due to power outage or restart of the device. The processor can access the persistent memory according to an instruction, and an access process does not involve an input/output (IO) operation, that is, an IO operation does not need to be performed for accessing the persistent memory.
[0008]In a possible implementation, the computer device further includes a memory controller, the at least two persistent memories are connected to the memory controller, and the memory controller is connected to the processor by the at least one management chip. The processor is configured to access the memory controller based on a logical address, and the memory controller is configured to translate the logical address into a physical address, and to access, based on the physical address, any one of the at least two persistent memories in communication with the processor. The logical address is an address used on the side of the processor, and the physical address is an address used on the side of the persistent memory, that is, different addresses are used by the processor and the persistent memory. The memory controller needs to translate an address, so that the processor accesses the persistent memory.
[0015]According to a second aspect, a data processing method is provided. The method is applied to a computer device. The device includes a processor, at least one management chip, and at least two persistent memories, the at least two persistent memories are connected to the processor by the at least one management chip, a communication state between each of the at least two persistent memories and the processor is controlled by the at least one management chip, and each persistent memory is configured to perform persistent storage on data. The method includes:
the processor receives a data processing request; and
the processor accesses, based on the data processing request, a target persistent memory that is in the at least two persistent memories and in communication with the processor, to read data from the target persistent memory or write data in the target persistent memory.
[0047]In an illustrative embodiment, the persistent memory 103 is a memory for which an input/output (IO) operation does not need to be performed. The IO operation is an operation that needs to be performed when a disk is accessed, and the IO operation is, for example, a track search operation or a sector search operation. Because the IO operation needs to be performed when the disk is accessed, efficiency of data processing performed by accessing the disk is low. However, because the IO operation does not need to be performed for accessing the persistent memory 103, efficiency of data processing performed by accessing the persistent memory 103 is high, and drive writes per day (DWPD) of the persistent memory 103 are further increased. Therefore, the persistent memory 103 has high reliability. When the device includes such a persistent memory 103 for which the IO operation does not need to be performed, if a service is interrupted because the device is shut down, data stored in the persistent memory 103 is not lost, and a recovery time object (RTO) is shortened because the efficiency of data processing performed by accessing the persistent memory 103 is high, thereby ensuring service stability.
[0048]In this embodiment, the disk is replaced with the persistent memory 103. Therefore, a new persistent storage manner is provided. In addition, because there are at least two persistent memories 103 in this embodiment of this application, a storage capacity used for persistent storage of the data can be expanded, thereby avoiding an insufficient storage capacity case. In addition, because the IO operation does not need to be performed for accessing the persistent memory 103, but the IO operation needs to be performed for accessing the disk, the IO operation can be not involved in a data processing process by using the persistent memory 103, thereby saving time for performing the IO operation, and improving data processing efficiency.
[0058]Referring to FIG. 9, in some implementations, the computer device further includes a disk, and the disk and the at least two persistent memories 103 are jointly configured to perform persistent storage on the data. Because the IO operation needs to be performed in a process of accessing the disk, and the IO operation does not need to be performed in a process of accessing the persistent memory 103, data processing efficiency during disk access is low. Illustratively, in this implementation, it may be determined, based on a processing requirement, whether to perform persistent storage on the data by using the persistent memory or the disk. For example, persistent storage is performed on the data by using the persistent memory 103 in response to a requirement that a data processing latency is lower than a threshold. Persistent storage is performed on the data by using the disk in response to that the data processing latency is allowed to be higher than the threshold. The threshold is not limited in this embodiment. Alternatively, in this implementation, it may be determined, based on a data type, whether to perform persistent storage on the data by using the persistent memory or the disk. Illustratively, persistent storage is performed on the data by using the persistent memory 103 in response to that the data type is a target type. Persistent storage is performed on the data by using the disk in response to that the data type is not a target type. There may be a plurality of data types, and the target type is at least one of the plurality of types. For example, the plurality of types include an integer type (int), a float type (float), and a character type (char), and the target type is int. Persistent storage is performed on the data by using the persistent memory 103 in response to that the data type is int. Persistent storage is performed on the data by using the disk in response to that the data type is float or char.
[0070]The persistent memory includes a label storage area (LSA) and data. Illustratively, a first byte range in the persistent memory is used to store the LSA, and a second byte range is used to perform persistent storage on the data. In some implementations, the first byte range includes bytes of a reference length starting from a start address of the persistent memory, and the second byte range includes other bytes after the first byte range. The reference length is not limited in this embodiment.
[0081]Illustratively, the persistent memory is configured to perform persistent storage on at least one data stripe, and one data stripe corresponds to verification data. The verification data and the data blocks are separately stored in different persistent memories persistently. When the second persistent memory that stores the data block is damaged, the data block stored in the second persistent memory is failed. Therefore, the processor obtains the verification data from the first persistent memory, and obtains another data block, other than the failed data block, in the data stripe from the another second persistent memory, so that the failed data block can be recovered based on the verification data and the another data block. The foregoing describes a case in which the persistent memory stores one data stripe. A case in which the persistent memory stores at least two data stripes is the same as that in the foregoing description. In some implementations, when the persistent memory stores at least two data stripes, verification data corresponding to the at least two data stripes are respectively located in different persistent memories.
[0082]In conclusion, in the embodiments of this application, the communication state between the persistent memory and the processor is controlled by the management chip, so that the processor is in communication with the at least two persistent memories. The processor can access the at least two persistent memories in communication with the processor, and the persistent memory can be configured to perform persistent storage on the data. Therefore, a storage capacity used for persistent storage of the data is expanded, and an insufficient storage capacity case is avoided. In addition, a new manner for persistent data storage is provided, which is different from a manner in which persistent storage is performed on the data by using only a disk in a related technology. (Emphasis added)
The specification provides the idea that communication between a processor and at least two persistent or non-volatile memories is facilitated via management chip. Each of the persistent memories is configured to perform persistent storage on data. Figures 2 and 3 shows a connection between management chip and persistent memory. Thus, the persistent memories, according to the specification appears to provide I/O operation (at least paragraph 0015), via I/O interface, such as the controller, or the management chip.
The persistent memories, as described in the specification, are configured to perform persistent storage, which stores data with certain storage type, or data stripe and its corresponding verification data.
The specification does not define what the I/O interface operations, or provides any details about interface, or any operations via interface. The specification only mentions that the IO operation does not need to be performed in a process of accessing the persistent memory. Thus, the specification does not provide sufficient details that one skill in the art can reasonably consider persistent memories do not require an input/output (IO) interface operation.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 5-9, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Fleisher et al (U.S. 11,288,122), hereinafter Fleisher, and in view of Okoda et al (U.S. 2002/0023195).
Regarding claim 1:
A computer device, comprising:
a central processing unit (CPU); at least one management chip [having an enabled state and a disabled state]; and at least two persistent memories operatively coupled to the CPU by the at least one management chip, wherein the at least two persistent memories do not require an input/output (IO) interface operation, each of the at least two persistent memories is configured to perform persistent storage on data; Fig. 1, Fleisher teaches the storage server includes multiple fabrics (management chip), each configured to provide a fully connected mesh topology (e.g., fully connected mesh network or fabric) that connects each of the plurality of IO controllers (CPUs) to each of the plurality of SSDs in a manner that provides full bandwidth of the SSDs for each connection. Fleisher teaches in Fig. 1, one or more controller 108 (CPUs) connects to multiple storage devices 150 via fabric 190A. Each of the controller 108 comprises a processor 215 or 216 (Fig. 2:14:15-25). The fabric 190A connects to multiple solid state drives (SSDs) 150A-150Z. The SSDs 150A-Z may be non-volatile memory (6:45-60). Each solid state drive (SSD) 150A-Z (also referred to as a solid state storage device) is a non-volatile storage device that uses integrated circuits to persistently store data (9:34-37). Each fabric 190A, 190B includes a management controller 115A, 115B soldered to the respective fabric 190A-B (9:65-67). The management controller(s) may determine which storage fabric 190A-B to make active for each of the IO controllers 108A-Y and for each of the SSDs 150A-Z. A management controller 115A-B may then send a message to one or more SSD 150A-Z and/or to one or more IO controller 108A-Y indicating which of the storage fabrics to connect to. At any time a management controller 115A-B may determine to make a different storage fabric active for an SSD and/or IO controller, and may send a new message notifying the SSD and/or IO controller to switch to that storage fabric (9:65 to 10:10). Thus, the persistent memories (SSDs) 150A-Z does not require I/O interface operation since the management chip already performed the I/O interface operations by assigning SSD to corresponding processor. Fleisher also suggests controller 108 may include central processing unit (CPU), graphical processing unit (GPU), 8:45-55.
the at least one management chip is configured to independently control a communication state between each persistent memory and the CPU, management chips may determine which storage fabric 190A-B to make active for each of the IO controllers 108A-Y and for each of the SSDs 150A-Z. A management controller 115A-B may then send a message to one or more SSD 150A-Z and/or to one or more IO controller 108A-Y indicating which of the storage fabrics to connect to. At any time a management controller 115A-B may determine to make a different storage fabric active for an SSD and/or IO controller, and may send a new message notifying the SSD and/or IO controller to switch to that storage fabric (9:65 to 10:10).
and the CPU is configured to access any one of the at least two persistent memories in communication with the CPU. Fleisher teaches in Fig. 1, one or more processors (controller 108) connects to multiple storage devices 150 via switch layers 110-112, which comprise a plurality of switches or bridges (8:15-25); the processor/controller 108 is configured to access the plurality of SSDs 150a-z (9:22-35).
However, Fleisher does not teach in response to the at least one management chip between one of the at least two persistent memories and the CPU being in the enabled state, the persistent memory is in communication with the CPU, in response to the at least one management chip between one of the at least two persistent memories and the CPU being in the disabled state, the persistent memory is not in communication with the CPU;
In an analogous art of storage management, Okada teaches in Fig. 1 and Fig. 2C,a switch device (Fig. 1, switch 4a, or Fig. 2C, switch 11) is between a controller (2a, or 2b), and storage device 8a. The switch includes first operation state (enable state) to connect controller (2a or 2b) to storage 8a, or a third operation state (disabled state), where for connecting none of the controllers 2a-2b to the storage 8a (¶0036).
Fleisher teaches the management chip (fabric 190) includes switch layer 110 (Fig .1) to facilitates communication between processor 108 and persistent memories 150A-Z (11:25-40). Okada teaches the idea of a switch include enable/disable state to connects or disconnects communication between a controller and a storage device as shown.
Thus, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Okada into the teaching of Fleisher to obtain the claimed limitation above. The motivation is to employ a known technique/apparatus of Okada into the system/method of Fleisher ready for improvement, to yield predictable result, which provide a disk array apparatus enabling a high data transfer rate at a reasonable cost with a high reliability as well as a switch circuit used for the disk array apparatus (Okada, ¶008).
Regarding claim 5:
The device according to claim 1, wherein the CPU includes a logic controller, and the logic controller is configured to control the communication state between each persistent memory and the CPU by controlling the at least one management chip. Fleisher, Fig. 2, controller 108 comprises processor/controller 215-216, and switch 220 configured to control the communication between the memory 150 and management chip/switch layer 112A/112B (14:30-60, 15:1-20).
Regarding claim 6:
The device according to claim 1, further comprising: at least two management chips, wherein the at least two management chips are separately coupled to the CPU, and any one of the at least two persistent memories is coupled to the CPU by any one of the at least two management chips. Fleisher, Fig. 2, first management chip switch 208A, second management chip switch 208B separately connects to processor/controller 108A, and SSD 150A-Z
Regarding claim 7:
The device according to claim 1, further comprising: at least two management chips including first and second management chips, Fleisher, Fig. 2, first switch/management chip 208A, second switch 212A.
the first management chip is coupled to the CPU, the second management chip is coupled to the first management chip, and any one of the at least two persistent memories is coupled to the CPU by the first management chip or the second management chip. SSD 150A connect to processor 215A via second management chip 212A and first management chip 208A.
Regarding claim 8:
The device according to claim 1, further comprising: a volatile memory operatively coupled to the CPU, wherein the CPU is further configured to access the volatile memory. Fleisher teaches the processor/controller 108 includes volatile memory (8:30-45).
Regarding claim 9:
A data processing method applied to a computer device having a central processing unit (CPU), at least one management chip [having an enabled state and a disabled state], and at least two persistent memories, wherein the at least two persistent memories are operatively coupled to the CPU by the at least one management chip, the at least two persistent memories do not require an input/output (IO) interface operation, a communication state between each of the at least two persistent memories and the CPU is independently controlled by the at least one management chip, and each persistent memory is configured to perform persistent storage on data, the method comprising: Fig. 1, Fleisher teaches the storage server includes multiple fabrics (management chip), each configured to provide a fully connected mesh topology (e.g., fully connected mesh network or fabric) that connects each of the plurality of IO controllers to each of the plurality of SSDs in a manner that provides full bandwidth of the SSDs for each connection. Fleisher teaches in Fig. 1, one or more controller 108 connects to multiple storage devices 150 via fabric 190A. Each of the controller 108 comprises a processor 215 or 216 (Fig. 2:14:15-25). The fabric 190A connects to multiple solid state drives (SSDs) 150A-150Z. The SSDs 150A-Z may be non-volatile memory (6:45-60). Each solid state drive (SSD) 150A-Z (also referred to as a solid state storage device) is a non-volatile storage device that uses integrated circuits to persistently store data (9:34-37). Each fabric 190A, 190B includes a management controller 115A, 115B soldered to the respective fabric 190A-B (9:65-67). The management controller(s) may determine which storage fabric 190A-B to make active for each of the IO controllers 108A-Y and for each of the SSDs 150A-Z. A management controller 115A-B may then send a message to one or more SSD 150A-Z and/or to one or more IO controller 108A-Y indicating which of the storage fabrics to connect to. At any time a management controller 115A-B may determine to make a different storage fabric active for an SSD and/or IO controller, and may send a new message notifying the SSD and/or IO controller to switch to that storage fabric (9:65 to 10:10). Thus, the persistent memories (SSDs) 150A-Z does not require I/O interface operation since the management chip already performed the I/O interface operations by assigning SSD to corresponding processor.
receiving, by the CPU, a data processing request; accessing, by the CPU and based on the data processing request, a target persistent memory in the at least two persistent memories and in communication with the CPU; and reading data from the target persistent memories or writing data to the target persistent memory, Fleisher teaches the processor/controller 108 is configured to read from and write to one or more of the plurality of SSD 150 (4:10-20). And the processor/controller 108 is configured to handle input/output I/O commands for host computing devices, such as read/write (8:60-67, 01:1-10).
However, Fleisher does not teach wherein in response to the at least one management chip between one of the at least two persistent memories and the CPU being in the enabled state, the persistent memory is in communication with the CPU, in response to the at least one management chip between one of the at least two persistent memories and the CPU being in the disabled state, the persistent memory is not in communication with the CPU;
In an analogous art of storage management, Okada teaches in Fig. 1 and Fig. 2C,a switch device (Fig. 1, switch 4a, or Fig. 2C, switch 11) is between a controller (2a, or 2b), and storage device 8a. The switch includes first operation state (enable state) to connect controller (2a or 2b) to storage 8a, or a third operation state (disabled state), where for connecting none of the controllers 2a-2b to the storage 8a (¶0036).
Fleisher teaches the management chip (fabric 190) includes switch layer 110 (Fig .1) to facilitates communication between processor 108 and persistent memories 150A-Z (11:25-40). Okada teaches the idea of a switch include enable/disable state to connects or disconnects communication between a controller and a storage device as shown.
Thus, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Okada into the teaching of Fleisher to obtain the claimed limitation above. The motivation is to employ a known technique/apparatus of Okada into the system/method of Fleisher ready for improvement, to yield predictable result, which provide a disk array apparatus enabling a high data transfer rate at a reasonable cost with a high reliability as well as a switch circuit used for the disk array apparatus (Okada, ¶008).
Regarding claim 13:
The method according to claim 9, wherein the CPU comprises a logic controller, and the method further comprises: controlling, by the logic controller, the communication state between each persistent memory and the CPU by controlling the at least one management chip. Fleisher, Fig. 2, controller 108 comprises processor/controller 215-216, and switch 220 configured to control the communication between the memory 150 and management chip/switch layer 112A/112B (14:30-60, 15:1-20).
Claims 2, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Fleisher et al (U.S. 11,288,122), hereinafter Fleisher, and in view of Okoda et al (U.S. 2022/0023195), and further in view of Perry et al (U.S 2020/0104253).
Regarding claim 2:
The device according to claim 1, further comprising: a memory controller, wherein the at least two persistent memories are operatively coupled to the memory controller, the memory controller is operatively coupled to the CPU by the at least one management chip,
the CPU is configured to access the memory controller based on a logical address, and the memory controller is configured to translate the logical address into a physical address, and access, based on the physical address, any one of the at least two persistent memories in communication with the CPU.
Fleisher does not teach the claimed limitations above. However, in an analogous art of memory management, Perry teaches a storage device 102, Fig. 1, comprises a controller 103 connect to a plurality of persistent memories 110-1 to 110-N. The controller is connected to a host 106 (Fig. 1). The host 106 can access data stored in the storage system 102 by providing a logical address, via the bus interface associated with the bus 112, to the controller 104, which, the controller 104 converts to a physical address. The controller 104 can access data and/or a particular storage location associated with the physical address and facilitate transferring data between the storage system 102 and the host 106 (¶0032).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Perry into the teaching of Fleisher to obtain the claimed limitations above. The motivation for doing so is to apply a known technique to a known device, of Fleisher, ready for improvement to yield predictable results, which provide I/O traffic between the host/processor and the persistent memories.
Regarding claim 10:
The method according to claim 9, wherein the device further comprises a memory controller, the at least two persistent memories are coupled to the memory controller, the memory controller is coupled to the CPU by the at least one management chip, and accessing the target persistent memory in the at least two persistent memories and in communication with the CPU comprises: accessing, by the CPU, the memory controller based on the data processing request and a logical address; translating, by the memory controller, the logical address into a physical address; and accessing, by the memory controller, the target persistent memory based on the physical address.
Fleisher does not teach the claimed limitations above. However, in an analogous art of memory management, Perry teaches a storage device 102, Fig. 1, comprises a controller 103 connect to a plurality of persistent memories 110-1 to 110-N. The controller is connected to a host 106 (Fig. 1). The host 106 can access data stored in the storage system 102 by providing a logical address, via the bus interface associated with the bus 112, to the controller 104, which, the controller 104 converts to a physical address. The controller 104 can access data and/or a particular storage location associated with the physical address and facilitate transferring data between the storage system 102 and the host 106 (¶0032).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Perry into the teaching of Fleisher to obtain the claimed limitations above. The motivation for doing so is to apply a known technique to a known device, of Fleisher, ready for improvement to yield predictable results, which provide I/O traffic between the host/processor and the persistent memories.
Claims 3, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Fleisher et al (U.S. 11,288,122), hereinafter Fleisher, and in view of Okoda et al (U.S. 2002/0023195), and further in view of Foley et al (U.S. 10,146,646).
Regarding claim 3:
The device according to claim 1, wherein the CPU includes a logic controller, the logic controller is configured to store redundant array of independent disks (RAID) information, and the CPU is configured to access, based on the RAID information stored in the logic controller, any one of the at least two persistent memories in communication with the CPU.
Fleisher teaches the idea of having a plurality of persistent memories arranged as a redundant array of independent disks (RAID) according to one of several RAID levels to provide different levels of redundancy and performance (Fleisher, 17:40-55). However, Fleisher does not teach the processor includes a logic controller configured to store RAID information.
In an analogous art of storage management, Foley teaches a storage processor in a data storage system may store configuration data for a particular RAID group (1:25-25). It is noted the examiner has interpreted that the processor is the logic controller, since the logic controller is a part of the processor.
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Foley to obtain the claimed limitations above. The motivation for doing so is to apply a known technique to a known device, of Fleisher, ready for improvement to yield predictable results, which provides different levels of redundancy and performance.
Regarding claim 11:
The method according to claim 9, wherein the CPU comprises a logic controller, the logic controller stores redundant array of independent disks (RAID) information, and accessing the target persistent memory in the at least two persistent memories and in communication with the CPU comprises: accessing, by the CPU and based on the data processing request and the RAID information stored in the logic controller, the target persistent memory in the at least two persistent memories and in communication with the CPU.
Fleisher teaches the idea of having a plurality of persistent memories arranged as a redundant array of independent disks (RAID) according to one of several RAID levels to provide different levels of redundancy and performance (Fleisher, 17:40-55). However, Fleisher does not teach the processor includes a logic controller configured to store RAID information.
In an analogous art of storage management, Foley teaches a storage processor in a data storage system may store configuration data for a particular RAID group (1:25-25). It is noted the examiner has interpreted that the processor is the logic controller, since the logic controller is a part of the processor.
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Foley to obtain the claimed limitations above. The motivation for doing so is to apply a known technique to a known device, of Fleisher, ready for improvement to yield predictable results, which provides different levels of redundancy and performance.
Claims 4, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Fleisher et al (U.S. 11,288,122), hereinafter Fleisher, and in view of Okoda et al (U.S. 2002/0023195), and further in view of Helmick et al (U.S. 2021/0132827).
Regarding claim 4:
The device according to claim 1, wherein the CPU includes a logic controller, the logic controller is configured to partition the at least two persistent memories to obtain regions and namespaces, and the CPU is configured to access at least one of the regions or the namespaces included in any one of the at least two persistent memories in communication with the CPU. Fleisher does not teach the claimed limitations above. However, in an analogous art of memory management, Helmick teaches in Fig. 4B, and corresponding text, a plurality of nonvolatile memory dies are arranged into endurance group EG (regions), each EG including multiple zones. In exemplary Fig. 4B, there are three zones in each EG, shown in both logical view 480 and physical view 481. EG1 is shown with 1 namespace NS1, similarly, EG2 is shown with NS2.
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Helmick to have a CPU includes a logic controller, the logic controller is configured to partition the at least two persistent memories to obtain regions and namespaces, and access the regions or namespaces. The motivation for doing so is to apply a known technique to a known device, of Fleisher, ready for improvement to yield predictable results, which offer greater control of how data is stored (Helmick, abstract).
Regarding claim 12:
The method according to claim 9, wherein the CPU comprises a logic controller, and the method further comprises: partitioning, by the logic controller, the at least two persistent memories to obtain regions and namespaces, wherein accessing the target persistent memory in the at least two persistent memories and in communication with the CPU comprises: accessing, by the CPU and based on the data processing request, at least one of the regions or the namespaces included in the target persistent memory in the at least two persistent memories and in communication with the CPU. Fleisher does not teach the claimed limitations above. However, in an analogous art of memory management, Helmick teaches in Fig. 4B, and corresponding text, a plurality of nonvolatile memory dies are arranged into endurance group EG (regions), each EG including multiple zones. In exemplary Fig. 4B, there are three zones in each EG, shown in both logical view 480 and physical view 481. EG1 is shown with 1 namespace NS1, similarly, EG2 is shown with NS2.
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Helmick to have a processor includes a logic controller, the logic controller is configured to partition the at least two persistent memories to obtain regions and namespaces, and access the regions or namespaces. The motivation for doing so is to apply a known technique to a known device, of Fleisher, ready for improvement to yield predictable results, which offer greater control of how data is stored (Helmick, abstract).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Fleisher et al (U.S. 11,288,122), hereinafter Fleisher, and in view of Okoda et al (U.S. 2022/0023195), and further in view of Muthiah et al (U.S. 2021/0382621).
Regarding claim 14:
The method according to claim 9, wherein the device further comprises a volatile memory coupled to the CPU, and the method further comprises: accessing, by the CPU, the volatile memory based on the data processing request; and reading data from the volatile memory or writing data to the volatile memory. Fleisher teaches the processor/controller 108 includes volatile memory (8:30-45).
However, Fleisher does not teach accessing, by the processor, the volatile memory based on the data processing request; and reading data from the volatile memory or writing data to the volatile memory. In analogous art of storage management, Muthiah teaches a storage configuration where a storage device connected to a processor 101, and memory 103 (Fig. 1); the memory 103 may include volatile memory, nonvolatile memory, or both (¶0025). Volatile memory 103 may be used to store data processed by host 104, or data received from the storage device 102 (¶0025).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Muthiah into the teaching of Fleisher to obtain the claimed limitation above. The motivation for doing so is to apply a known technique/apparatus, into the device of Fleisher, ready for improvement, to yield predictable results.
Claim 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Fleisher et al (U.S. 11,288,122), hereinafter Fleisher, and in view of Okoda et al (U.S. 2002/0023195), and further in view of Shitomi et al (U.S. 2013/0024634).
Regarding claim 15:
A computer system, comprising:
a first computer device, wherein the first computer device comprises:
a central processing unit (CPU); at least one management chip [having an enabled state and disabled state]; and at least two persistent memories operatively coupled to the CPU by the at least one management chip, wherein the at least two persistent memories do not require an input/output (IO) operation, each of the at least two persistent memories is configured to perform persistent storage on data, the at least one management chip is configured to independently control a communication state between each persistent memory and the CPU, Fig. 1, Fleisher teaches the storage server includes multiple fabrics (management chip), each configured to provide a fully connected mesh topology (e.g., fully connected mesh network or fabric) that connects each of the plurality of IO controllers to each of the plurality of SSDs in a manner that provides full bandwidth of the SSDs for each connection. Fleisher teaches in Fig. 1, one or more controller 108 connects to multiple storage devices 150 via fabric 190A. Each of the controller 108 comprises a processor 215 or 216 (Fig. 2:14:15-25). The fabric 190A connects to multiple solid state drives (SSDs) 150A-150Z. The SSDs 150A-Z may be non-volatile memory (6:45-60). Each solid state drive (SSD) 150A-Z (also referred to as a solid state storage device) is a non-volatile storage device that uses integrated circuits to persistently store data (9:34-37). Each fabric 190A, 190B includes a management controller 115A, 115B soldered to the respective fabric 190A-B (9:65-67). The management controller(s) may determine which storage fabric 190A-B to make active for each of the IO controllers 108A-Y and for each of the SSDs 150A-Z. A management controller 115A-B may then send a message to one or more SSD 150A-Z and/or to one or more IO controller 108A-Y indicating which of the storage fabrics to connect to. At any time a management controller 115A-B may determine to make a different storage fabric active for an SSD and/or IO controller, and may send a new message notifying the SSD and/or IO controller to switch to that storage fabric (9:65 to 10:10). Thus, the persistent memories (SSDs) 150A-Z does not require I/O interface operation since the management chip already performed the I/O interface operations by assigning SSD to corresponding processor.
the CPU is configured to access any one of the at least two persistent memories in communication with the CPU; Fleisher teaches the processor/controller 108 is configured to read from and write to one or more of the plurality of SSD 150 (4:10-20). And the processor/controller 108 is configured to handle input/output I/O commands for host computing devices, such as read/write (8:60-67, 01:1-10).
and a second computer device, wherein the second computer device comprises a CPU; at least one management chip [having the enabled state and disabled state]; and at least two persistent memories operatively coupled to the CPU by the at least one management chip, wherein the at least two persistent memories do not require an input/output (IO) operation, each of the at least two persistent memories is configured to perform persistent storage on data, the at least one management chip is configured to independently control a communication state between each persistent memory and the CPU, Fig. 1, Fleisher teaches the storage server includes multiple fabrics (management chip), each configured to provide a fully connected mesh topology (e.g., fully connected mesh network or fabric) that connects each of the plurality of IO controllers to each of the plurality of SSDs in a manner that provides full bandwidth of the SSDs for each connection. Fleisher teaches in Fig. 1, one or more controller 108 connects to multiple storage devices 150 via fabric 190A. Each of the controller 108 comprises a processor 215 or 216 (Fig. 2:14:15-25). The fabric 190A connects to multiple solid state drives (SSDs) 150A-150Z. The SSDs 150A-Z may be non-volatile memory (6:45-60). Each solid state drive (SSD) 150A-Z (also referred to as a solid state storage device) is a non-volatile storage device that uses integrated circuits to persistently store data (9:34-37). Each fabric 190A, 190B includes a management controller 115A, 115B soldered to the respective fabric 190A-B (9:65-67). The management controller(s) may determine which storage fabric 190A-B to make active for each of the IO controllers 108A-Y and for each of the SSDs 150A-Z. A management controller 115A-B may then send a message to one or more SSD 150A-Z and/or to one or more IO controller 108A-Y indicating which of the storage fabrics to connect to. At any time a management controller 115A-B may determine to make a different storage fabric active for an SSD and/or IO controller, and may send a new message notifying the SSD and/or IO controller to switch to that storage fabric (9:65 to 10:10). Thus, the persistent memories (SSDs) 150A-Z does not require I/O interface operation since the management chip already performed the I/O interface operations by assigning SSD to corresponding processor.
the CPU is configured to access any one of the at least two persistent memories in communication with the CPU, Fleisher teaches the processor/controller 108 is configured to read from and write to one or more of the plurality of SSD 150 (4:10-20). And the processor/controller 108 is configured to handle input/output I/O commands for host computing devices, such as read/write (8:60-67, 01:1-10).
However, Fleisher does not teach in response to the at least one management chip between one of the at least two persistent memories and the CPU being in the enabled state, the persistent memory is in communication with the CPU, in response to the at least one management chip between one of the at least two persistent memories and the CPU being in the disabled state, the persistent memory is not in communication with the CPU;
In an analogous art of storage management, Okada teaches in Fig. 1 and Fig. 2C,a switch device (Fig. 1, switch 4a, or Fig. 2C, switch 11) is between a controller (2a, or 2b), and storage device 8a. The switch includes first operation state (enable state) to connect controller (2a or 2b) to storage 8a, or a third operation state (disabled state), where for connecting none of the controllers 2a-2b to the storage 8a (¶0036).
Fleisher teaches the management chip (fabric 190) includes switch layer 110 (Fig .1) to facilitates communication between processor 108 and persistent memories 150A-Z (11:25-40). Okada teaches the idea of a switch include enable/disable state to connects or disconnects communication between a controller and a storage device as shown.
Thus, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Okada into the teaching of Fleisher to obtain the claimed limitation above. The motivation is to employ a known technique/apparatus of Okada into the system/method of Fleisher ready for improvement, to yield predictable result, which provide a disk array apparatus enabling a high data transfer rate at a reasonable cost with a high reliability as well as a switch circuit used for the disk array apparatus (Okada, ¶008).
The combination of Fleisher and Okada does not teach wherein the first computer device is configured to send data to the second computer device, and the second computer device is configured to store the data, received from the first computer device, in a persistent memory of the second computer device. In an analogous of multi-storage management, Shitomi teaches the idea that a first storage apparatus transmits data to a second storage apparatus, for storing the data in storage drives of the second storage apparatus (¶0066, Fig. 4, storage drives 171).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Shitomi into the teaching of Fleisher to obtain the claimed limitations above. The motivation for doing so is to The motivation for doing so is to apply a known technique/apparatus, into the device of Fleisher, ready for improvement, to yield predictable results, which provides data redundancy.
Regarding claim 16:
The system according to claim 15, wherein the data, sent to the second computer device, is stored in a persistent memory of the first computer device. Shitomi, Fig. 4, data is stored in drives 17 of the first storage apparatus (¶0091).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Fleisher et al (U.S. 11,288,122 hereinafter Fleisher, and in view of Okoda et al (U.S. 2022/0023195), and further in view of Shitomi et al (U.S. 2013/0024634), and further in view of Perry et al (U.S 2020/0104253).
Regarding claim 17:
The system according to claim 15, wherein the first computer device further comprises: a memory controller, wherein the at least two persistent memories are operatively coupled to the memory controller, the memory controller is operatively coupled to the CPU by the at least one management chip, the CPU is configured to access the memory controller based on a logical address, and the memory controller is configured to translate the logical address into a physical address, and access, based on the physical address, any one of the at least two persistent memories in communication with the CPU. Fleisher does not teach the claimed limitations above. However, in an analogous art of memory management, Perry teaches a storage device 102, Fig. 1, comprises a controller 103 connect to a plurality of persistent memories 110-1 to 110-N. The controller is connected to a host 106 (Fig. 1). The host 106 can access data stored in the storage system 102 by providing a logical address, via the bus interface associated with the bus 112, to the controller 104, which, the controller 104 converts to a physical address. The controller 104 can access data and/or a particular storage location associated with the physical address and facilitate transferring data between the storage system 102 and the host 106 (¶0032).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Perry into the teaching of Fleisher to obtain the claimed limitations above. The motivation for doing so is to apply a known technique to a known device, of Fleisher, ready for improvement to yield predictable results, which provide I/O traffic between the host/processor and the persistent memories.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Fleisher et al (U.S. 11,288,122), hereinafter Fleisher, and in view of Okoda et al (U.S. 2022/0023195), and further in view of Shitomi et al (U.S. 2013/0024634), and further in view of Foley et al (U.S. 10,146,646).
Regarding claim 18:
The system according to claim 15, wherein the CPU includes a logic controller, the logic controller is configured to store redundant array of independent disks (RAID) information, and the CPU is configured to access, based on the RAID information stored in the logic controller, any one of the at least two persistent memories in communication with the CPU.
Fleisher teaches the idea of having a plurality of persistent memories arranged as a redundant array of independent disks (RAID) according to one of several RAID levels to provide different levels of redundancy and performance (Fleisher, 17:40-55). However, Fleisher does not teach the processor includes a logic controller configured to store RAID information.
In an analogous art of storage management, Foley teaches a storage processor in a data storage system may store configuration data for a particular RAID group (1:25-25). It is noted the examiner has interpreted that the processor is the logic controller, since the logic controller is a part of the processor.
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Foley to obtain the claimed limitations above. The motivation for doing so is to apply a known technique to a known device, of Fleisher, ready for improvement to yield predictable results, which provides different levels of redundancy and performance.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Fleisher et al (U.S. 11,288,122), hereinafter Fleisher, and in view of Okoda et al (U.S. 202/0023195), and further in view of Shitomi et al (U.S. 2013/0024634), and further in view of Lee et al (U.S. 12,541,458).
Regarding claim 19:
The combination of Fleisher does not teach the device according to claim 2, wherein the CPU interacts with the memory controller by using a computer express link (CXL) technology. However, in an analogous art of storage operation management, Lee teaches a storage device comprises a controller in communication with a host device, including a central processing unit (CPU), a processor, a microprocessor (Fig. 1, 3:30-35), based on compute express link (CXL) interface (4:1-20).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Lee into the teaching of Fleisher to consider applying CXL technology in communication links between computer components of Fleisher. The motivation for doing so is to apply a known technique into the device ready for improvement of Fleisher to yield predictable result, which improves data transmission speed.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Fleisher et al (U.S. 11,288,122), hereinafter Fleisher, and in view of Okoda et al (U.S. 2002/0023195), and further in view of Shitomi et al (U.S. 2013/0024634), and further in view of Muthiah et al (U.S. 2021/0382621)
Regarding claim 20:
The device according to claim 2, wherein each of the at least tow persistent memories comprises a label storage area (LSA) and data, the LSA comprises a region label and a namespace label, and the memory controller indexes the data based on the LSA information. The combination of Fleisher does not teach the claimed limitations above. However, in an analogous art of storage management, Muthiah teaches a storage controller stores configuration information, as metadata in nonvolatile memory, indicating one or more physical blocks are assigned to different logical regions according to characteristics of corresponding namespace, , based on mapping 316 of namespaces received from host. Fig. 3, the mapping (LSA) 316 and 318 comprises namespace label, and address ranges/regions, and data is indexed using the mappings, ¶0026, ¶0039,¶0045-¶0047, fig. 4 and corresponding text.
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Muthiah into the teaching of Fleisher have a LSA of metadata/mapping regions to have a details control information of the storage and data. The motivation for doing so is to apply a known technique into the device ready for improvement of Fleisher to yield predictable result.
Response to Arguments
Applicant’s arguments with respect to exemplary independent claim 1 have been considered but are moot in light of new grounds of rejection presented above. Claims 9 and 15 are rejected under similar rationale cited in claim 1, and the details office action above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yeung et al (U.S. 2021/0334226) teaches a storage controller is responsible for configuring and operating locally PCIe attached Ethernet device. Each of the Storage Controller Ethernet ports is attached to an Ethernet switch in a fully redundant configuration. The storage controller can have 1 to “N” Storage Controllers, each with 1 to “M” PCIe Ports associated with it.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KHOA D DOAN/Primary Examiner, Art Unit 2133