Detailed Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Furuta (USPGPUB 2013/0015996).
Regarding claim 1, Furuta discloses a successive approximation analog-to-digital converter (figs. 1, 3, 9, 10, 14, 16, 18) that generates a digital output signal corresponding to an analog input signal, the successive approximation analog-to-digital converter comprising: a capacitive digital-to-analog converter (fig. 7; paragraphs 0038, 0039, 0043) that samples an analog signal corresponding to the analog input signal and that generates an analog output signal corresponding to a sampling result and a digital input; a comparator (11, figs. 1, 3, 9, 10, 14, 16, 18) that compares the analog output signal and a comparison standard voltage; and a control circuit (12, figs. 1, 3, 9, 10, 14, 16, 18) that generates the digital input corresponding to a comparison result obtained by the comparator, wherein the capacitive digital-to-analog converter (fig. 7; paragraphs 0038, 0039, 0043) includes an input node that receives the analog signal, a plurality of capacitors (see the capacitors in figs. 1, 3, 9, 10, 14, 16, 18), and an adjustment capacitor (variable capacitor; Vc11,.. Vc14) charged with an adjustment voltage, and supplies the analog signal to the plurality of capacitors through the input node to sample the analog signal, the comparator performs successive approximation of the analog output signal in relation to each bit from a most significant bit to a least significant bit of the digital output signal and the comparison standard voltage (abstract; figs. 1, 3, 9, 10, 14, 16, 18), the control circuit (figs. 1, 3, 9, 10, 14, 16, 18) generates the digital output signal in reference to a result of the successive approximation by the comparator, and the adjustment capacitor supplies a voltage corresponding to the adjustment voltage to the input node before next sampling is performed after the successive approximation (figs. 1, 3, 9, 10, 14, 16, 18; abstract).
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Regarding claim 2, Furuta discloses a successive approximation analog-to-digital converter (figs. 1, 3, 9, 10, 14, 16, 18) wherein the capacitive digital-to-analog converter (fig. 7; paragraphs 0038, 0039, 0043) further includes an output node connected to another end of each of the plurality of capacitors (figs. 1, 3, 9, 10, 14, 16, 18) and configured to output the analog output signal, and the adjustment capacitor (abstract) supplies the voltage corresponding to the adjustment voltage to the input node when one end of the adjustment capacitor is connected to the input node and another end of the adjustment capacitor is connected to the output node supplied with a circuit standard voltage (figs. 1, 3, 9, 10, 14, 16, 18).
Regarding claim 3, Furuta discloses a successive approximation analog-to-digital converter (figs. 1, 3, 9, 10, 14, 16, 18) further comprising: a switch (note the switched in figs. 1, 3, 9, 10, 14, 16, 18) arranged between a circuit that outputs the analog signal and the input node, wherein the other end of each of the plurality of capacitors is connected to the input node when the switch is off and the one end of the adjustment capacitor is connected to the input node (figs. 1, 3, 9, 10, 14, 16, 18; abstract) .
Regarding claim 4, Furuta discloses a successive approximation analog-to-digital converter (figs. 1, 3, 9, 10, 14, 16, 18) wherein the capacitive digital-to-analog converter (fig. 7; paragraphs 0038, 0039, 0043) supplies a circuit standard voltage or a reference voltage to one end of each of the plurality of capacitors according to the digital input to thereby generate the analog output signal, and the adjustment capacitor is charged with the adjustment voltage corresponding to the comparison standard voltage and the reference voltage when the reference voltage is supplied to one end of the adjustment capacitor and the comparison standard voltage is supplied to another end of the adjustment capacitor during the sampling of the analog signal (figs. 1, 3, 9, 10, 14, 16, 18).
Regarding claim 5, Furuta discloses a successive approximation analog-to-digital converter (figs. 1, 3, 9, 10, 14, 16, 18), wherein the capacitive digital-to-analog converter further includes an output node connected to another end of each of the plurality of capacitors and configured to output the analog output signal, and the other end of the adjustment capacitor is charged with the adjustment voltage when the other end of the adjustment capacitor is connected to the output node supplied with the comparison standard voltage during the sampling of the analog signal.
Regarding claim 6, Furuta discloses a successive approximation analog-to-digital converter (figs. 1, 3, 9, 10, 14, 16, 18), wherein the capacitive digital-to-analog converter supplies a circuit standard voltage or a reference voltage to one end of each of the plurality of capacitors (see figs. 1, 3, 9, 10, 14, 16, 18 for the plurality of capacitors) according to the digital input to thereby generate the analog output signal, and the adjustment voltage is a voltage one half of the reference voltage (figs. 1, 3, 9, 10, 14, 16, 18).
Regarding claim 7, Furuta discloses a successive approximation analog-to-digital converter (figs. 1, 3, 9, 10, 14, 16, 18), wherein capacitance of the adjustment capacitor (variable capacitor; Vc11,.. Vc14) is combined capacitance of the plurality of capacitors (abstract; paragraph 0035).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEAN BRUNER JEANGLAUDE whose telephone number is (571)272-1804. The examiner can normally be reached Monday-Thursday 7:00 AM-5:00 PM.
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/JEAN B JEANGLAUDE/Primary Examiner, Art Unit 2845