DETAILED ACTION
This action is responsive to the application filed 25 Mar 2024 and the Information Disclosure Statement filed 9 Aug 2024. Claims 1 - 20 are pending. Claims 1, 13, & 19 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9Sep2022 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 2, 4, 5, 7 – 9, 12 – 14, and 18 – 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Nitzan, et al, U.S. Patent Application Publication 2024/0312528 (“Nitzan”).
Regarding claim 1, Nitzan teaches:
A system comprising: a memory device comprising a plurality of wordline groups, each of the plurality of wordline groups comprising memory cells; and a memory controller operatively coupled to the memory device, the memory controller performing operations comprising: (Nitzan, fig 2, “[0023] Storage device 120 provides non-volatile storage functionality for use by the host 110. Storage device 120 may include an integrated circuit comprising a controller communicatively coupled to a memory such as an SSD or HDD. … The memory 140 may be organized into pages, blocks, planes, die and chips. [0027] FIG. 2 shows a threshold voltage distribution of an exemplary quadruple-level cell (QLC) of a flash memory device”; a computer system with controllers and memory array; the array is organized into pages, or “wordline groups”, that each page with 16 data settings is read then tested for accuracy).
determining a select read level voltage offset for a select read level voltage used to read data from memory cells of a select wordline group of the plurality of wordline groups; (Nitzan, fig 3, “[0029] For each condition, different read thresholds may be chosen to achieve the lowest BER after a READ operation. Thus, the read thresholds of a target page in the NAND device may be estimated repeatedly during the device life cycle in order to maintain high read performance and benefit from an efficient read flow with low latency that avoids soft bit (SB) decoding as much as possible. [0030] Stage 310: Retrieve input thresholds for target row stored in controller. These input thresholds may be default factory settings written in the device firmware, or obtained from a history table stored in the controller. The input thresholds are then used for a page READ. Stage 320: A first hard bit (HB) or hard decision decoding is then performed on the read data. If the previous HB decoding stage fails, apply QT to obtain new thresholds, and page READ.”; a hard read is performed, the hard read step if the read based on thresholds fails, then a QT (quick training algorithm) process is applied (see paragraph 0017) on the page being read (i.e. the page is a group of wordlines); here the QT step 330 provides the “voltage offset” to read the multiple data levels shown in figure 2; data from page read are then tested in HB2 which looks at the offset read level voltages for the page based on degradation, etc).
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determining, by a wordline group machine-learning model, a plurality of predicted select read level voltage offsets for the select read level voltage used to read data from memory cells of other wordline groups of the plurality of wordline groups; (Nitzan, fig 2, 3, 4C, “[0030] Stage 340: A second HB decoding is performed. … [0031] From read flow 300, it can be seen that the QT threshold estimation capability at stage 330 is very important for maintaining HB decoding success (e.g. non-failure) at stage 340. [0022] QT involves the mock reading of data that is obtained during processing of a read command, e.g. a read flow, for estimating threshold voltages at a current stage of processing the read command. The mock reads are reads at fixed predetermined thresholds, termed ‘mocks’ that are chosen based on offline optimization and database training. According to embodiments of the present disclosure, processing mock reading data features prior to QT read thresholds estimation improves estimation accuracy and consequently improves hard decision decoding performance and QoS of the memory device. [0041] In a further embodiment of the present disclosure, the estimated 15 QLC thresholds V isxi can be obtained from a deep-neural network (DNN) as depicted in Fig 4C which shows a multi-layer perception (MLP) DNN.”; a second HB reading based on the best available QT offsets; that these QT offsets are developed over time during a read commands (which can be any page); the chosen QT offsets are then modified and applied to the system for the next page read requiring HB decode 2. Note: the claim language does not require that only a single “Wordline Group” be used to train the entire chip. Nitzan’s process uses each subsequent reading fail to update and provide the appropriate read voltage offset for the appropriate data voltage level of figure 2; fig 4C demonstrates that a single input can cascade through the multiple hidden layers to produce an output layer).
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based on the plurality of predicted select read level voltage offsets and the select read level voltage offset, (Nitzan, fig 3, “Stage 350: If the previous HB decoding stage fails, a soft decision or soft bit (SB) decoding stage with 2-bit information (SB2) is performed. [0016] The SB decoding requires a large number of READ operations and may induce high latency.”; as stated above, the system builds a continuous histogram when the HB decoding fails; that each of the 16 levels is modeled separately; that the QT process takes the initial read voltage from the entire page; and multiple correlation features are considered to build a histogram to avoided an SB reading process; from ppp 0041 above, the DNN can have multiple stages).
determining, by a plurality of read level machine-learning models, a plurality of predicted other read level voltage offsets for other read level voltages used to read data from memory cells of at least one wordline group of the plurality of wordline groups; and (Nitzan, fig 3, 4A,4B, 5, “[0033] QT with feature processing. [0034] A method to estimate the read thresholds of a target row uses a linear combination of the distribution of threshold voltages such as mock histogram data (mock histogram bins), as reference above. For the four pages of a QLC NAND device, the estimation V^(15x1) of the 15 QLC read thresholds is: [0035] According to an embodiment of the present disclosure, a more advanced estimator is proposed that processes the mock histogram features and creates nonlinear transformations of the mock histogram as additional features. ..”; with QLC, each level is modeled as shown in figure 5 which shows modeling of the upper, middle, and lower pages of the QLC data; as shown below, these QLC data have individual “features” that are tested to find the best fit for that particular data read level).
updating, based on the plurality of predicted select read level voltage offsets and the plurality of predicted other read level voltage offsets, a look-up table that comprises a set of read level voltage offsets used with one or more read level voltages to read data from one or more memory cells of the plurality of wordline groups. (Nitzan, fig 4A/4B, 5, “[0035] For example, in some cases a polynomial fit between the mock histogram values and the optimal thresholds is more appropriate than a linear fit as used by QT. The polynomial fit can be implemented by using G but not by using H. The advantage of a polynomial fit compared to linear fit to data that behaves in a nonlinear fashion is demonstrated in FIG. 4B. [0044] According to a further embodiment of the present disclosure, the cross validation results of feature processing using QT, QT CORR, and QT CORR K that chooses K features from the overall 152 features… The 16 mock histogram H features for QLC are always selected. The feature selection method used is an iterative permutation feature importance (PFI). [0041] The MLP can be used to accurately estimate the read thresholds using some input features. According to another embodiment of the present disclosure, the DNN input features can be the computed histogram H from the mock reads and the processed nonlinear transformations G.”; that data are collected continuously (as expected with a histogram) that the data in the histogram are estimated for each of the 15 QLC thresholds; that the incoming data are fitted to either linear regression or polynomial regression to obtain the best fit; the system tests each of the features over time to emphasize the most important feature in finding thresholds; the MLP DNN updates the estimates based on new input readings, and from new transformations G).
Regarding claim 2, Nitzan teaches The system of claim 1, wherein the select read level voltage offset is determined by: performing a scan operation on at least one memory cell of the select wordline group to determine the select read level voltage offset. (Nitzan, fig 2, 3, “[0030] fig. 3… Stage 310: Retrieve input thresholds for target row stored in controller. These input thresholds may be default factory settings written in the device firmware, or obtained from a history table stored in the controller. The input thresholds are then used for a page READ.”; that a page is read (a word line group), that the page is initially read using initial inputs; if those inputs fail, then an “iterative permutation feature importance” process is used to select the estimated best threshold for the page).
Regarding claim 4, Nitzan teaches The system of claim 1, wherein the wordline group machine-learning model comprises at least one of an artificial neural network or a linear regression model. (Nitzan, fig 4A, “[0034] The coefficient matrix X15x 16, may be determined using a simple linear regression 410, as exemplified in FIG. 4A. [0019] A linear QT estimator or a deep-neural network (DNN) QT is used for estimation of the optimal read thresholds given the processed features.”; linear regression and DNN can estimate and predict threshold voltages).
Regarding claim 5, Nitzan teaches The system of claim 1, wherein each of the plurality of read level machine-learning models comprises at least one of an artificial neural network or a linear regression model. (Nitzan, fig 5, “[0035] Then, for the 15 thresholds, we obtain the following estimator V 15xl = Y1sxM • GMxl, where V isxi is the estimation results of 15 QLC thresholds, GMxI is the vector of linear and nonlinear transformations of the histogram values H obtained from mock reads, and Y 1 sxM is the linear estimator coefficients matrix,”; that 16 models are required for QLC thresholds to find the best voltage value using multiple feature processing).
Regarding claim 7, Nitzan teaches The system of claim 1, wherein the select read level voltage corresponds to a highest read level voltage used to read data from memory cells of the plurality of wordline groups. (Nitzan, fig 3, “[0029] For each condition, different read thresholds may be chosen to achieve the lowest BER after a READ operation. Thus, the read thresholds of a target page in the NAND device may be estimated repeatedly during the device life cycle in order to maintain high read performance and benefit from an efficient read flow with low latency that avoids soft bit (SB) decoding as much as possible. [0030] Stage 310: Retrieve input thresholds for target row stored in controller. These input thresholds may be default factory settings written in the device firmware, or obtained from a history table stored in the controller. The input thresholds are then used for a page READ. Stage 320: A first hard bit (HB) or hard decision decoding is then performed on the read data. If the previous HB decoding stage fails, apply QT to obtain new thresholds, and page READ. [0027] The threshold voltage distribution for each of the sixteen states of the QLC is shown in the sixteen lobes 0-15 of FIG. 2. Reading from the various pages of the QLC requires using various threshold voltages.”; a hard read is performed, that each of the QLC values can be tested using the process to find the linear regression; the hard read step if the read based on thresholds fails, then a QT (quick training algorithm) process is applied (see paragraph 0017) on the page being read (i.e. the page is a group of wordlines); here the QT step 330 provides the “voltage offset” to read the multiple data levels shown in figure 2; data from page read are then tested in HB2 which looks at the offset read level voltages for the page based on degradation, etc).
Regarding claim 8, Nitzan teaches The system of claim 7, wherein the other read level voltages correspond to lower read level voltages used to read data from memory cells of the plurality of wordline groups. (Nitzan, fig 3, “[0029] For each condition, different read thresholds may be chosen to achieve the lowest BER after a READ operation. Thus, the read thresholds of a target page in the NAND device may be estimated repeatedly during the device life cycle in order to maintain high read performance and benefit from an efficient read flow with low latency that avoids soft bit (SB) decoding as much as possible. [0030] Stage 310: Retrieve input thresholds for target row stored in controller. These input thresholds may be default factory settings written in the device firmware, or obtained from a history table stored in the controller. The input thresholds are then used for a page READ. Stage 320: A first hard bit (HB) or hard decision decoding is then performed on the read data. If the previous HB decoding stage fails, apply QT to obtain new thresholds, and page READ. [0027] The threshold voltage distribution for each of the sixteen states of the QLC is shown in the sixteen lobes 0-15 of FIG. 2. Reading from the various pages of the QLC requires using various threshold voltages.”; a hard read is performed, that each of the QLC values can be tested using the process to find the linear regression; the hard read step if the read based on thresholds fails, then a QT (quick training algorithm) process is applied (see paragraph 0017) on the page being read (i.e. the page is a group of wordlines); here the QT step 330 provides the “voltage offset” to read the multiple data levels shown in figure 2; data from page read are then tested in HB2 which looks at the offset read level voltages for the page based on degradation, etc).
Regarding claim 9, Nitzan teaches The system of claim 1, wherein the look-up table comprises a plurality of tables each corresponding to a different wordline group of the plurality of wordline groups. (Nitzan, fig 1, “[0025] The internal memory 170 may be configured to store data such system metadata, mapping tables and bad block lists. In some embodiments, such data may also be stored in the local external memory 150”; that mapping data can treat different word groups differently, in this case at least one block is “bad” and would have different storage requirements).
Regarding claim 12, Nitzan teaches The system of claim 1, wherein each of the memory cells is a triple-level cell (TLC) or a quad-level cell (QLC). (Nitzan, fig 2, “[0027] FIG. 2 shows a threshold voltage distribution of an exemplary quadruple-level cell (QLC) of a flash memory device”; a system can operate with QLC).
Regarding claim 13, Nitzan teaches:
A method comprising: (Nitzan, fig 2, “[0023] Storage device 120 provides non-volatile storage functionality for use by the host 110. Storage device 120 may include an integrated circuit comprising a controller communicatively coupled to a memory such as an SSD or HDD. … The memory 140 may be organized into pages, blocks, planes, die and chips. [0027] FIG. 2 shows a threshold voltage distribution of an exemplary quadruple-level cell (QLC) of a flash memory device”; a computer system with controllers and memory array; the array is organized into pages, or “wordline groups”, that each page with 16 data settings is read then tested for accuracy).
determining a select read level voltage offset for a select read level voltage used to read data from a select memory cell of a memory device; (Nitzan, fig 3, “[0029] For each condition, different read thresholds may be chosen to achieve the lowest BER after a READ operation. Thus, the read thresholds of a target page in the NAND device may be estimated repeatedly during the device life cycle in order to maintain high read performance and benefit from an efficient read flow with low latency that avoids soft bit (SB) decoding as much as possible. [0030] Stage 310: Retrieve input thresholds for target row stored in controller. These input thresholds may be default factory settings written in the device firmware, or obtained from a history table stored in the controller. The input thresholds are then used for a page READ. Stage 320: A first hard bit (HB) or hard decision decoding is then performed on the read data. If the previous HB decoding stage fails, apply QT to obtain new thresholds, and page READ.”; a hard read is performed, the hard read step if the read based on thresholds fails, then a QT (quick training algorithm) process is applied (see paragraph 0017) on the page being read (i.e. the page is a group of wordlines); here the QT step 330 provides the “voltage offset” to read the multiple data levels shown in figure 2; data from page read are then tested in HB2 which looks at the offset read level voltages for the page based on degradation, etc).
determining, by a machine-learning cascade model, a plurality of predicted read level voltage offsets based on the select read level voltage offset, (Nitzan, fig 2, 3, 4C, “[0030] Stage 340: A second HB decoding is performed. … [0031] From read flow 300, it can be seen that the QT threshold estimation capability at stage 330 is very important for maintaining HB decoding success (e.g. non-failure) at stage 340. [0022] QT involves the mock reading of data that is obtained during processing of a read command, e.g. a read flow, for estimating threshold voltages at a current stage of processing the read command. The mock reads are reads at fixed predetermined thresholds, termed ‘mocks’ that are chosen based on offline optimization and database training. According to embodiments of the present disclosure, processing mock reading data features prior to QT read thresholds estimation improves estimation accuracy and consequently improves hard decision decoding performance and QoS of the memory device. [0041] In a further embodiment of the present disclosure, the estimated 15 QLC thresholds V isxi can be obtained from a deep-neural network (DNN) as depicted in Fig 4C which shows a multi-layer perception (MLP) DNN.”; a second HB reading based on the best available QT offsets; that these QT offsets are developed over time during a read commands (which can be any page); the chosen QT offsets are then modified and applied to the system for the next page read requiring HB decode 2. Note: the claim language does not require that only a single “Wordline Group” be used to train the entire chip. Nitzan’s process uses each subsequent reading fail to update and provide the appropriate read voltage offset for the appropriate data voltage level of figure 2; fig 4C demonstrates that a single input can cascade through the multiple hidden layers to produce an output layer).
the machine-learning cascade model comprising a plurality of stages, each stage of the plurality of stages being associated with a different memory cell attribute of the memory device and comprising a set of machine-learning models, (Nitzan, fig 3, “Stage 350: If the previous HB decoding stage fails, a soft decision or soft bit (SB) decoding stage with 2-bit information (SB2) is performed. [0016] The SB decoding requires a large number of READ operations and may induce high latency.”; as stated above, the system builds a continuous histogram when the HB decoding fails; that each of the 16 levels is modeled separately; that the QT process takes the initial read voltage from the entire page; and multiple correlation features are considered to build a histogram to avoided an SB reading process; from ppp 0041 above, the DNN can have multiple stages).
each machine-learning model of the set of machine-learning models being configured to receive an input read level voltage offset and being trained to determine two or more predicted read level voltage offsets for different values of the different memory cell attribute based on the input read level voltage offset; and (Nitzan, fig 3, 4A,4B, 5, “[0033] QT with feature processing. [0034] A method to estimate the read thresholds of a target row uses a linear combination of the distribution of threshold voltages such as mock histogram data (mock histogram bins), as reference above. For the four pages of a QLC NAND device, the estimation V^(15x1) of the 15 QLC read thresholds is: [0035] According to an embodiment of the present disclosure, a more advanced estimator is proposed that processes the mock histogram features and creates nonlinear transformations of the mock histogram as additional features. ..”; with QLC, each level is modeled as shown in figure 5 which shows modeling of the upper, middle, and lower pages of the QLC data; as shown below, these QLC data have individual “features” that are tested to find the best fit for that particular data read level).
updating, based on the plurality of predicted read level voltage offsets, a look-up table that comprises a set of read level voltage offsets used to read data from one or more memory cells of the memory device. (Nitzan, fig 4A/4B, 5, “[0035] For example, in some cases a polynomial fit between the mock histogram values and the optimal thresholds is more appropriate than a linear fit as used by QT. The polynomial fit can be implemented by using G but not by using H. The advantage of a polynomial fit compared to linear fit to data that behaves in a nonlinear fashion is demonstrated in FIG. 4B. [0044] According to a further embodiment of the present disclosure, the cross validation results of feature processing using QT, QT CORR, and QT CORR K that chooses K features from the overall 152 features… The 16 mock histogram H features for QLC are always selected. The feature selection method used is an iterative permutation feature importance (PFI). [0041] The MLP can be used to accurately estimate the read thresholds using some input features. According to another embodiment of the present disclosure, the DNN input features can be the computed histogram H from the mock reads and the processed nonlinear transformations G.”; that data are collected continuously (as expected with a histogram) that the data in the histogram are estimated for each of the 15 QLC thresholds; that the incoming data are fitted to either linear regression or polynomial regression to obtain the best fit; the system tests each of the features over time to emphasize the most important feature in finding thresholds; the MLP DNN updates the estimates based on new input readings, and from new transformations G).
Regarding claim 14, Nitzan teaches The method of claim 13, wherein the different memory cell attribute comprises a wordline group. (Nitzan, fig 2, “[0023] Storage device 120 provides non-volatile storage functionality for use by the host 110. Storage device 120 may include an integrated circuit comprising a controller communicatively coupled to a memory such as an SSD or HDD. … The memory 140 may be organized into pages, blocks, planes, die and chips. [0027] FIG. 2 shows a threshold voltage distribution of an exemplary quadruple-level cell (QLC) of a flash memory device”; a computer system with controllers and memory array; the array is organized into pages, or “wordline groups”, that each page with 16 data settings is read then tested for accuracy; a “word-line group” can comprise any grouping of word-lines from memory cells with a common wordline, to entire blocks of memory).
Regarding claim 18, Nitzan teaches The method of claim 13, wherein the look-up table comprises a plurality of tables each corresponding to a different set of memory cell attributes. (Nitzan, fig 4 and 5 (all), “[0041] The input features to the DNN may be G the generalized mock histogram vector that may include various nonlinear transformations of the original histogram values, and P additional features, e.g. physical row number, program/erase cycle count, read disturb count, mock thresholds, etc.”; that the histogram look-up tables can vary based on the input of the wordline physical row number, PEC, etc).
Regarding claim 19, Nitzan teaches:
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: (Nitzan, fig 2, “[0023] Storage device 120 provides non-volatile storage functionality for use by the host 110. Storage device 120 may include an integrated circuit comprising a controller communicatively coupled to a memory such as an SSD or HDD. … The memory 140 may be organized into pages, blocks, planes, die and chips. [0027] FIG. 2 shows a threshold voltage distribution of an exemplary quadruple-level cell (QLC) of a flash memory device. [0046] Additionally, in the foregoing, all recitation of “command,” “action” or “function” should be taken to be based on algorithms and instructions stored on a non-transitory computer-readable medium, that, when executed by a processor”; a computer system with controllers and memory array; the array is organized into pages, or “wordline groups”, that each page with 16 data settings is read then tested for accuracy; that non-transitory CR storage can hold executable code to implement the processes).
determining a select read level voltage offset for a select read level voltage used to read data from a select memory cell of a memory device; (Nitzan, fig 3, “[0029] For each condition, different read thresholds may be chosen to achieve the lowest BER after a READ operation. Thus, the read thresholds of a target page in the NAND device may be estimated repeatedly during the device life cycle in order to maintain high read performance and benefit from an efficient read flow with low latency that avoids soft bit (SB) decoding as much as possible. [0030] Stage 310: Retrieve input thresholds for target row stored in controller. These input thresholds may be default factory settings written in the device firmware, or obtained from a history table stored in the controller. The input thresholds are then used for a page READ. Stage 320: A first hard bit (HB) or hard decision decoding is then performed on the read data. If the previous HB decoding stage fails, apply QT to obtain new thresholds, and page READ.”; a hard read is performed, the hard read step if the read based on thresholds fails, then a QT (quick training algorithm) process is applied (see paragraph 0017) on the page being read (i.e. the page is a group of wordlines); here the QT step 330 provides the “voltage offset” to read the multiple data levels shown in figure 2; data from page read are then tested in HB2 which looks at the offset read level voltages for the page based on degradation, etc).
determining, by a machine-learning cascade model, a plurality of predicted read level voltage offsets based on the select read level voltage offset, (Nitzan, fig 2, 3, 4C, “[0030] Stage 340: A second HB decoding is performed. … [0031] From read flow 300, it can be seen that the QT threshold estimation capability at stage 330 is very important for maintaining HB decoding success (e.g. non-failure) at stage 340. [0022] QT involves the mock reading of data that is obtained during processing of a read command, e.g. a read flow, for estimating threshold voltages at a current stage of processing the read command. The mock reads are reads at fixed predetermined thresholds, termed ‘mocks’ that are chosen based on offline optimization and database training. According to embodiments of the present disclosure, processing mock reading data features prior to QT read thresholds estimation improves estimation accuracy and consequently improves hard decision decoding performance and QoS of the memory device. [0041] In a further embodiment of the present disclosure, the estimated 15 QLC thresholds V isxi can be obtained from a deep-neural network (DNN) as depicted in Fig 4C which shows a multi-layer perception (MLP) DNN.”; a second HB reading based on the best available QT offsets; that these QT offsets are developed over time during a read commands (which can be any page); the chosen QT offsets are then modified and applied to the system for the next page read requiring HB decode 2. Note: the claim language does not require that only a single “Wordline Group” be used to train the entire chip. Nitzan’s process uses each subsequent reading fail to update and provide the appropriate read voltage offset for the appropriate data voltage level of figure 2; fig 4C demonstrates that a single input can cascade through the multiple hidden layers to produce an output layer).
the machine-learning cascade model comprising a plurality of stages, each stage of the plurality of stages being associated with a different memory cell attribute of the memory device and comprising a set of machine-learning models, (Nitzan, fig 3, “Stage 350: If the previous HB decoding stage fails, a soft decision or soft bit (SB) decoding stage with 2-bit information (SB2) is performed. [0016] The SB decoding requires a large number of READ operations and may induce high latency.”; as stated above, the system builds a continuous histogram when the HB decoding fails; that each of the 16 levels is modeled separately; that the QT process takes the initial read voltage from the entire page; and multiple correlation features are considered to build a histogram to avoided an SB reading process; from ppp 0041 above, the DNN can have multiple stages).
each machine-learning model of the set of machine-learning models being configured to receive an input read level voltage offset and being trained to determine two or more predicted read level voltage offsets for different values of the different memory cell attribute based on the input read level voltage offset; and (Nitzan, fig 3, 4A,4B, 5, “[0033] QT with feature processing. [0034] A method to estimate the read thresholds of a target row uses a linear combination of the distribution of threshold voltages such as mock histogram data (mock histogram bins), as reference above. For the four pages of a QLC NAND device, the estimation V^(15x1) of the 15 QLC read thresholds is: [0035] According to an embodiment of the present disclosure, a more advanced estimator is proposed that processes the mock histogram features and creates nonlinear transformations of the mock histogram as additional features. ..”; with QLC, each level is modeled as shown in figure 5 which shows modeling of the upper, middle, and lower pages of the QLC data; as shown below, these QLC data have individual “features” that are tested to find the best fit for that particular data read level).
updating, based on the plurality of predicted read level voltage offsets, a look-up table that comprises a set of read level voltage offsets used to read data from one or more memory cells of the memory device. (Nitzan, fig 4A/4B, 5, “[0035] For example, in some cases a polynomial fit between the mock histogram values and the optimal thresholds is more appropriate than a linear fit as used by QT. The polynomial fit can be implemented by using G but not by using H. The advantage of a polynomial fit compared to linear fit to data that behaves in a nonlinear fashion is demonstrated in FIG. 4B. [0044] According to a further embodiment of the present disclosure, the cross validation results of feature processing using QT, QT CORR, and QT CORR K that chooses K features from the overall 152 features… The 16 mock histogram H features for QLC are always selected. The feature selection method used is an iterative permutation feature importance (PFI). [0041] The MLP can be used to accurately estimate the read thresholds using some input features. According to another embodiment of the present disclosure, the DNN input features can be the computed histogram H from the mock reads and the processed nonlinear transformations G.”; that data are collected continuously (as expected with a histogram) that the data in the histogram are estimated for each of the 15 QLC thresholds; that the incoming data are fitted to either linear regression or polynomial regression to obtain the best fit; the system tests each of the features over time to emphasize the most important feature in finding thresholds; the MLP DNN updates the estimates based on new input readings, and from new transformations G).
Regarding claim 20, Nitzan teaches The non-transitory computer-readable storage medium of claim 19, wherein the select read level voltage offset is determined by: performing a scan operation on at least one memory cell of the select wordline group to determine the select read level voltage offset. (Nitzan, fig 3, 7, “[0045] [0045] FIG. 7 illustrates an exemplary flow diagram of a method 700 for reading data from a flash memory using threshold voltage estimation”; that data can be read from a memory array and input into the DNN for processing).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 3 and 15 – 17 are rejected under 35 U.S.C. 103 as being unpatentable over Nitzan in view of Ahn, et al, U.S. Patent Application Publication 2024/0126453 (“Ahn”).
Regarding claim 3, Nitzan teaches the system of claim 2.
Nitzan does not explicitly teach:
wherein the scan operation comprises: applying different read level voltages to the at least one memory cell; determining whether an individual one of the different read level voltages reaches a center of valley; and
determining that the select read level voltage offset has been reached in response to determining that the individual one of the different read level voltages reaches the center of valley..
Ahn teaches:
wherein the scan operation comprises: applying different read level voltages to the at least one memory cell; determining whether an individual one of the different read level voltages reaches a center of valley; and (Ahn, fig 16, “[0165] FIG. 16 is a graph illustrating a valley search operation and a method of obtaining a plurality of points, according to an embodiment.”; that multiple points can be collected from a cell between two different outcomes, that a valley search can give a point most likely to minimize read errors).
determining that the select read level voltage offset has been reached in response to determining that the individual one of the different read level voltages reaches the center of valley. (Ahn, fig 16-20, “[0172] From among the first to fifth points Pa, Pb, Pc, Pd, and Pe, the third point Pc corresponding to the smallest memory cell count value may correspond to the valley, and a point corresponding to the valley may be referred to as a valley point.”; that Pc is the most likely threshold voltage to minimize read errors. Figures 17-20 show other examples of valley search).
In view of the teachings of Ahn it would have been obvious for a person of ordinary skill in the art to apply the teachings of Ahn to Nitzan before the effective filing date of the claimed invention in order to teach reading MLC memory cells. The teachings of AHN, in the same or in a similar field of endeavor with Nitzan, can combine AHN’s valley search of linear regression with Nitzan’s linear regression modeling. The two elements merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 15, Nitzan teaches the method of claim 13.
Nitzan does not explicitly teach wherein the different memory cell attribute comprises an operating temperature..
Ahn teaches wherein the different memory cell attribute comprises an operating temperature. (Ahn, fig 10, “[0134] Referring to FIG. 10, threshold voltage distributions of the plurality of memory cells may be degraded due to various factors. The various factors may include, but not be limited to, charge leakage, read disturbance, program disturbance, coupling between adjacent memory cells, temperature change, voltage change, and the degradation of memory cells due to repeated program and erase operations.”; a memory cell can change its performance due to operating temperatures).
In view of the teachings of Ahn it would have been obvious for a person of ordinary skill in the art to apply the teachings of Ahn to Nitzan before the effective filing date of the claimed invention in order to teach reading MLC memory cells. The teachings of AHN, in the same or in a similar field of endeavor with Nitzan, can combine Ahn’s reasons for memory cell deviations with Nitzan’s linear regression modeling. The two elements merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 16, Nitzan teaches the method of claim 13.
Nitzan does not explicitly teach wherein the different memory cell attribute comprises an elapsed programming time of data..
Ahn teaches wherein the different memory cell attribute comprises an elapsed programming time of data. (Ahn, fig 10, “[0252] Case 2 may schematically show the threshold voltage distributions TVDl, TVD2, TVD3, and TVD4 of the plurality of selection memory cells, according to the coupling effects of adjacent memory cells in a state of the non-volatile memory 120, after a predetermined retention period.”; a memory cell can change its performance after a predetermined retention period).
In view of the teachings of Ahn it would have been obvious for a person of ordinary skill in the art to apply the teachings of Ahn to Nitzan before the effective filing date of the claimed invention in order to teach reading MLC memory cells. The teachings of AHN, in the same or in a similar field of endeavor with Nitzan, can combine Ahn’s reasons for memory cell deviations with Nitzan’s linear regression modeling. The two elements merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 17, Nitzan teaches the method of claim 13.
Nitzan does not explicitly teach wherein the different memory cell attribute comprises a program erase count..
Ahn teaches wherein the different memory cell attribute comprises a program erase count. (Ahn, fig 10, “[0134] Referring to FIG. 10, threshold voltage distributions of the plurality of memory cells may be degraded due to various factors. The various factors may include, but not be limited to, charge leakage, read disturbance, program disturbance, coupling between adjacent memory cells, temperature change, voltage change, and the degradation of memory cells due to repeated program and erase operations.”; a memory cell can change its performance due to program erase counts).
In view of the teachings of Ahn it would have been obvious for a person of ordinary skill in the art to apply the teachings of Ahn to Nitzan before the effective filing date of the claimed invention in order to teach reading MLC memory cells. The teachings of AHN, in the same or in a similar field of endeavor with Nitzan, can combine Ahn’s reasons for memory cell deviations with Nitzan’s linear regression modeling. The two elements merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claims 6 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Nitzan in view of Cohen, et al, U.S. Patent Application Publication 20140229131 (“Cohen”).
Regarding claim 6, Nitzan teaches the system of claim 1.
Nitzan does not explicitly teach wherein the wordline group machine-learning model and the plurality of read level machine-learning models are trained during manufacture of the system..
Cohen teaches wherein the wordline group machine-learning model and the plurality of read level machine-learning models are trained during manufacture of the system. (Cohen, fig 1, “[0028] However, the optimal threshold of a target row is not known during NAND device operation as device operation and history would have shifted thresholds from their initial factory values or from the values written to the controller firmware. [0045] The read command is executed using initial thresholds that may be default factory settings written in the device firmware, or obtained from a history table stored in the controller.”; a system can have initial settings and can vary those settings as the life cycle of the chip progresses).
In view of the teachings of Cohen it would have been obvious for a person of ordinary skill in the art to apply the teachings of Cohen to Nitzan before the effective filing date of the claimed invention in order to teach reading MLC memory cells. The teachings of Cohen, in the same or in a similar field of endeavor with Nitzan, can combine Cohen’s initial and periodic evaluation of memory cells and Nitzan’s less explicit timelines for evaluation. The two elements merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 11, Nitzan teaches the system of claim 1.
Nitzan does not explicitly teach wherein the operations are performed periodically to update the look-up table..
Cohen teaches wherein the operations are performed periodically to update the look-up table. (Cohen, fig 4, “[0225] Embodiments represented by FIG. 4 adjust at least one read threshold in response to an uncorrectable (e.g. hard-decision decode) error. Embodiments represented by FIGS. 5A, 5B, 5C, and 6 adjust at least one read threshold in response to any one or more of manufacturing characterization, initial use, a timer (e.g. periodic, irregular, or random), a bit error rate that is above a threshold, and an uncorrectable (e.g. hard-decision decode) error.”; that periodic tests can be run on memory cells to adjust one or more thresholds).
In view of the teachings of Cohen it would have been obvious for a person of ordinary skill in the art to apply the teachings of Cohen to Nitzan before the effective filing date of the claimed invention in order to teach reading MLC memory cells. The teachings of Cohen, in the same or in a similar field of endeavor with Nitzan, can combine Cohen’s initial and periodic evaluation of memory cells and Nitzan’s less explicit timelines for evaluation. The two elements merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Nitzan in view of LEEM, et al, U.S. Patent Application Publication 20150019922 (“LEEM”).
Nitzan teaches the system of claim 1.
Nitzan teaches wherein the set of read level voltage offsets of the look-up table is organized according to bins, and (Nitzan, fig 4A/4B, 5, “[0035] For example, in some cases a polynomial fit between the mock histogram values and the optimal thresholds is more appropriate than a linear fit as used by QT. The polynomial fit can be implemented by using G but not by using H. The advantage of a polynomial fit compared to linear fit to data that behaves in a nonlinear fashion is demonstrated in FIG. 4B. [0044] According to a further embodiment of the present disclosure, the cross validation results of feature processing using QT, QT CORR, and QT CORR K that chooses K features from the overall 152 features… The 16 mock histogram H features for QLC are always selected. The feature selection method used is an iterative permutation feature importance (PFI). [0041] The MLP can be used to accurately estimate the read thresholds using some input features. According to another embodiment of the present disclosure, the DNN input features can be the computed histogram H from the mock reads and the processed nonlinear transformations G.”; that data are collected continuously (as expected with a histogram) that the data in the histogram are estimated for each of the 15 QLC thresholds based on updated read values).
Nitzan does not explicitly teach:
wherein the updating of the look-up table based on the plurality of predicted select read level voltage offsets and the plurality of predicted other read level voltage offsets comprises: identifying a plurality of bins of the look-up table corresponding to the select read level voltage offset; and
replacing, in the set of read level voltage offsets, values of the plurality of bins with respective ones of the plurality of predicted other read level voltage offsets..
LEEM teaches:
wherein the updating of the look-up table based on the plurality of predicted select read level voltage offsets and the plurality of predicted other read level voltage offsets comprises: identifying a plurality of bins of the look-up table corresponding to the select read level voltage offset; and (LEEM, fig 1, “[0019] As described more below, priority manager 112 includes logic and/or features that may generate or provide an MRR table that includes priority-based or count-ranked entries that may be dynamically or adaptively assigned. According to some examples, the priority-based or count-based entries may be adaptively assigned based on such criteria as program/erase cycle counts associated with memory cells of non-volatile memory 130, MRR tables used by other non-volatile memories, historical operating parameters for non-volatile memory 130, possible defects or operating characteristics associated with one or more memory cells of non-volatile memory 130 such as program disturb or intrinsic charge loss or success of given entries to recover from a read error.”; a memory that can build a Memory Read Reference (MRR) table based on multiple factors such as PEC, “operating parameters, or other sources of defects).
replacing, in the set of read level voltage offsets, values of the plurality of bins with respective ones of the plurality of predicted other read level voltage offsets. (LEEM, fig 1, “[0052] In some examples, in addition to assigning priorities based on program/erase cycle counts, priority manager 112 may include logic and/or features to assign higher priorities based on an amount of time the non-volatile memory may be powered on or receiving power. For these examples, longer power on times may indicate exposure to elevated operating temperatures for the non-volatile memory. Elevated operating temperatures may increase the likelihood of intrinsic charge loss for one or more memory cells”; that based on operating parameters, such as temperature, the MRR may draw from different sub-tables to create a “priority based” MRR to decode read voltage level).
In view of the teachings of LEEM it would have been obvious for a person of ordinary skill in the art to apply the teachings of LEEM to Nitzan before the effective filing date of the claimed invention in order to teach reading MLC memory cells. The teachings of LEEM, in the same or in a similar field of endeavor with Nitzan, can combine LEEM’s continuously updated read references based on 5 factors for reading memory cells and Nitzan’s less explicit initial and updated histogram for reading memory cells. The two elements merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Conclusion
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825