DETAILED ACTION
1. Applicant’s Amendment filed 7/30/2026 has been reviewed and placed of record in the file.
Response to Arguments
2. Applicant’s arguments, see “Applicant Arguments/Remarks Made in an Amendment”, filed 07/30/2026, with respect to (i) the rejection(s) of claim(s) 19 under 35 U.S.C. §102(a)(1) over Cho’s Fig. 9 Embodiment, (ii) the rejection(s) of claim(s) 19-20 under 35 U.S.C. §102(a)(2) over Johnson and (iii) the rejection of claims 19, 21, 24, and 27-29 under 35 U.S.C. & 103 over Saito in view of Johnson have been fully considered and are persuasive. Therefore, the rejections have been withdrawn.
However, (a) the nonstatutory double patenting rejection over claim 1 of U.S. Patent No. 11,942,503 and claims 12-15 over claim 1 of U.S. Patent No. 11,942,503 in view of Saito U.S. Patent Application Publication 20120074327 and (b) the rejections of claims 19-20, 24 and 27 under 35 U.S.C. §102(a)(1) over Cho’s Fig. 13 Embodiment stay. Furthermore, (c) upon further consideration and search, new ground of rejections is made in view of Mo et al. U.S. Patent Application Publication 20120013780.
Double Patenting
3. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/forms/. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
4. Claim 11 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,942,503. Although the conflicting claims are not identical, they are not patentably distinct from each other because patent claim 1, albeit a method claim, recites basically all limitations of application claim 11.
Specifically, the conflicting claims are listed below,
Application Claim
Patent Claim
11. A flat panel image sensor comprising:
1. A method of constructing a flat panel image sensor, the method comprising:
a plurality of image sensor chips mounted on a substrate, wherein the substrate includes a plurality of openings, wherein each of the plurality of openings enables access to at least one image sensor unit of the plurality of image sensor units, and wherein each image sensor chip includes at least one chip contact array and wherein at least one contact of each image sensor unit is accessible through at least one opening;
mounting a plurality of image sensor chips on a substrate, wherein the substrate includes a plurality of openings, wherein each of the plurality of openings enables access to at least one image sensor unit of the plurality of image sensor units, and wherein each image sensor chip includes at least one chip contact array and wherein at least one contact of each image sensor unit is accessible through at least one opening, wherein the openings are through-holes that each correspond to a single contact of the plurality of image sensor units, optionally wherein the openings are electrically conductive through vias;
a printed circuit board (“PCB”) attached to the substrate, wherein the PCB includes a plurality of PCB contact arrays, wherein each PCB contact array is in alignment with and in electrical connection with a corresponding chip contact array using electrically adhesive paste;
attaching a printed circuit board (“PCB”) to the substrate, wherein the PCB includes a plurality of PCB contact arrays, wherein each PCB contact array is configured to be placed in alignment and in electrical connection with a corresponding chip contact array;
forming on each PCB contact array and each chip contact array a ball of electrically conductive adhesive paste;
wherein the substrate and the PCB are aligned so that each ball of electrically conductive adhesive paste is in contact with one electrical contact pad to form an image sensor assembly.
aligning the substrate and the PCB so that each ball of electrically conductive adhesive paste is in contact with one electrical contact pad to form an image sensor assembly; and
curing the image sensor assembly.
5. Claims 12-15 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,942,503 in view of Saito U.S. Patent Application Publication 20120074327 (now of record).
Referring to claim 12, patent claim 1 recites the plurality of image sensor chips as detailed above for claim 11, but does not disclose that the plurality of image sensor chips are arranged in a pattern such that no single seam between chips extends across the entire flat panel image sensor.
Saito, in disclosing a flat panel image sensor (1107, Fig. 8, para [64] (paragraph(s) [0064])) comprising a plurality of image sensor chips (51/109-54/109, para [64, 74], wherein “chips” are cut from a wafer (para [6, 64]) and wherein 109 is for “connection”, para [64]), teaches that the plurality of image sensor chips are arranged in a pattern such that no single seam between (adjacent) chips extends across the entire flat panel image sensor for the purposes of forming a large area flat panel image sensor (para [6, 64] and see Fig. 8).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the plurality of image sensor chips arranged in a pattern such that no single seam between chips would have extended across the entire flat panel image sensor. One would have been motivated to make such a modification in view of the teachings in Saito to form a working large area flat panel image sensor.
Furthermore, referring to claims 13 and 14, although patent claim 1 in view of Saito does not specifically disclose relative dimensions as claimed, the claimed relative dimensions (claim 13: wherein the plurality of chips vary in one or both of size and shape, claim 14: wherein the plurality of chips do not vary in shape and size) will not support the patentability of subject matter encompassed by the prior art (Saito appears disclose wherein the plurality of chips do not vary in shape and size) unless there is evidence indicating such relative dimensions are critical. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation"; MPEP 2144.05.
Referring to claim 15, Saito further disclose that each image sensor chip is comprised of one image sensor units, meeting the claim limitation “one or more image sensor units”.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
6. Claims 19-20, 24 and 27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho U.S. Patent Application Publication 2012/0188422 A1 (the ‘422 reference, now of record).
The reference discloses in Fig. 13 and related text an image sensor unit and a large area flat panel image sensor as claimed.
Referring to claim 19, the ‘422 reference discloses an image sensor unit (62/SC1/SC2/CC1/CC2, Fig. 13) comprising:
an array (pixel array 62 (1-1) para [54] (paragraph(s) [0054])) of image sensing pixels, arranged in a plurality of rows and a plurality of columns, wherein each pixel is individually addressable (para [42]);
a row control circuitry (SC1, para [43]) in communication with each row of pixels in the array via a row addressing line, wherein the row control circuitry is capable of selectively addressing one or more of the plurality of rows;
a column control circuitry (column readout circuit SC2, para [43]) in communication with each column of pixels in the array via a column addressing line, wherein the column control circuitry is capable of selectively addressing one or more of the plurality of columns; and
a unit controller (control circuit block CC1/CC2, para [53-57]) in communication with the row control circuitry (SC1) and the column control circuitry (SC2), wherein the unit controller (CC1/CC2) is configured to specify selective readout of one or more pixel readout signals by instructing the row control circuitry to address one or more specific rows of the array and by instructing the column control circuitry to address one or more specific columns of the array (para [53-57]; specifically, para [53]: circuit blocks CC1 and CC2 …for selectively routing signals, para [55]: CC1 block may shift the row select signals (i.e., “to address one or more specific rows”), para [56]: CC2 may be used to map lines such as lines 72 to a selected subset of output lines 40 (wherein the selected output lines 40 are vertical column lines (see Fig. 13), i.e. “to address one or more specific columns”)).
Referring to claim 20, the reference further discloses a memory configured to store pixel locations, wherein the pixel locations specify one or more of a pre-defined readout pattern of pixels, [pixels marked for repair,] and pixels marked to skip readout (para [32], memory from processing circuitry, ”Image data that has been captured by camera module 12 may be processed and stored”, para [54]: “some of the sensors (e.g., inactivated sensors) may be bypassed using circuits CC1” ) (wherein “image data” is equivalent to claim “pixel locations” and claim “pre-defined readout pattern of pixels”, and “bypassed” is equivalent to claim “to skip readout”).
Referring to claim 24, the reference further discloses that the image sensor unit (62/SC1/SC2/CC1/CC2) is combined with one or more additional image sensor units (62/SC1/SC2/CC1/CC2) to form a large area flat panel of image sensor units.
Referring to claim 27 and using the same reference characters, interpretations, and citations as detailed above for claims 19 and 24 where applicable, the ‘422 reference discloses a large area flat panel image sensor comprising:
a plurality of image sensor units (62/SC1/SC2/CC1/CC2, Fig. 13) that are each independently selectable, configurable, and accessible (“independently controlled”, para [54]), wherein each image sensor unit comprises:
an array (62) of image sensing pixels, arranged in a plurality of rows and a plurality of columns, wherein each pixel is individually addressable;
a row control circuitry (SC1) in communication with each row of pixels in the array via a row addressing line, wherein the row control circuitry is capable of selectively addressing one or more of the plurality of rows;
a column control circuitry (SC2) in communication with each column of pixels in the array via a column addressing line, wherein the column control circuitry is capable of selectively addressing one or more of the plurality of columns; and
a unit controller (CC1/CC2) in communication with the row control circuitry and the column control circuitry, wherein the unit controller is configured to specify selective readout of one or more pixel readout signals by instructing the row control circuitry to address one or more specific rows of the array and by instructing the column control circuitry to address one or more specific columns of the array.
7. Claim 19 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mo et al. U.S. Patent Application Publication 2012/0013780 A1 (the ‘780 reference).
Referring to claim 19, the ‘780 reference discloses an image sensor unit (600, Fig. 6, para [46]) comprising:
an array (602, Fig. 6) of image sensing pixels (100 (Fig. 1), para [12]), arranged in a plurality of rows and a plurality of columns, wherein each pixel is individually addressable (para [47]);
a row control circuitry (row decoder 606, para [47]) in communication with each row of pixels in the array via a row addressing line, wherein the row control circuitry is capable of selectively addressing one or more of the plurality of rows (para [47]);
a column control circuitry (column decoder 610, para [47]) in communication with each column of pixels in the array via a column addressing line, wherein the column control circuitry is capable of selectively addressing one or more of the plurality of columns (para [47]); and
a unit controller (timing and control unit 612) in communication with the row control circuitry (606) and the column control circuitry (610), wherein the unit controller (612) is configured to specify selective readout of one or more pixel readout signals by instructing the row control circuitry to address one or more specific rows of the array and by instructing the column control circuitry to address one or more specific columns of the array (para [47]: “unit 612 can instruct row decoder 606 and column decoder 610 to select an appropriate row and column line in order to read a particular pixel”).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
8. Claims 19, 21, 24, and 27-29 are rejected under 35 U.S.C. §103 as being unpatentable over Saito U.S. Patent Application Publication 20120074327 (the ‘327 reference, now of record) in view of Mo et al. U.S. Patent Application Publication 2012/0013780 A1 (the ‘780 reference).
Referring to claims 19, 24 and 27, Saito ‘327 discloses and image sensor unit (51/109, Fig. 8, para [74, 64] where 109 is for “connection” (para [64])), the image sensor unit being combined with one or more additional image sensor units (52/109-54/109, para [74]) to form a large area flat panel of image sensor units, and a large area flat panel image sensor comprising a plurality of image sensor units (51/109-54/109) that are each independently selectable, configurable, and accessible (para [8]), but does not disclose that each image sensor unit comprises: an array of image sensing pixels, arranged in a plurality of rows and a plurality of columns, wherein each pixel is individually addressable; a row control circuitry in communication with each row of pixels in the array via a row addressing line, wherein the row control circuitry is capable of selectively addressing one or more of the plurality of rows; a column control circuitry in communication with each column of pixels in the array via a column addressing line, wherein the column control circuitry is capable of selectively addressing one or more of the plurality of columns; and a unit controller in communication with the row control circuitry and the column control circuitry, wherein the unit controller is configured to specify selective readout of one or more pixel readout signals by instructing the row control circuitry to address one or more specific rows of the array and by instructing the column control circuitry to address one or more specific columns of the array.
Mo, in disclosing an image sensor unit, teaches that the image sensor unit (600, Fig. 6, para [46]) comprising: an array (602, Fig. 6) of image sensing pixels (100 (Fig. 1), para [12]), arranged in a plurality of rows and a plurality of columns, wherein each pixel is individually addressable (para [47]); a row control circuitry (row decoder 606, para [47]) in communication with each row of pixels in the array via a row addressing line, wherein the row control circuitry is capable of selectively addressing one or more of the plurality of rows (para [47]); a column control circuitry (column decoder 610, para [47]) in communication with each column of pixels in the array via a column addressing line, wherein the column control circuitry is capable of selectively addressing one or more of the plurality of columns (para [47]); and a unit controller (timing and control unit 612) in communication with the row control circuitry (606) and the column control circuitry (610), wherein the unit controller (612) is configured to specify selective readout of one or more pixel readout signals by instructing the row control circuitry to address one or more specific rows of the array and by instructing the column control circuitry to address one or more specific columns of the array (para [47]: “unit 612 can instruct row decoder 606 and column decoder 610 to select an appropriate row and column line in order to read a particular pixel”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the ‘327 reference’s each of image sensor units (51/109-54/109) to have comprised an array (602) of image sensing pixels (100), arranged in a plurality of rows and a plurality of columns, wherein each pixel is individually addressable; a row control circuitry (606) in communication with each row of pixels in the array via a row addressing line, wherein the row control circuitry is capable of selectively addressing one or more of the plurality of rows; a column control circuitry (610) in communication with each column of pixels in the array via a column addressing line, wherein the column control circuitry is capable of selectively addressing one or more of the plurality of columns; and a unit controller (612) in communication with the row control circuitry (606) and the column control circuitry (610), wherein the unit controller (612) is configured to specify selective readout of one or more pixel readout signals by instructing the row control circuitry to address one or more specific rows of the array and by instructing the column control circuitry to address one or more specific columns of the array (para [47]).
One would have been motivated to make such a modification in view of the teachings in Mo to form a working large area flat panel image sensor comprising working image sensor units.
Referring to claim 21, the ‘327 reference further discloses at least one signal amplifier (31, para [37]) configured to output amplified signals.
Referring to claim 28, the ‘327 reference further discloses that each image sensor unit (of units 51/109-54/109) is disposed on one of a plurality of image sensor chips (cut from a wafer, para [6, 64]).
Referring to claim 29, Fig. 8 of the ‘327 reference depicts that the plurality of chips (forming image sensors 51/109-54/109) are arranged in a pattern such that no single seam between (adjacent) chips extends across the entire large area flat panel image sensor.
Response to Arguments
9. Applicant’s arguments with the nonstatutory obviousness-type double patenting with respect to claim 1, filed 30 July 2026, have been fully considered but they are not persuasive.
While it is true that, as pointed out by applicant, patent claim 1 recites the openings to be "through-holes that each correspond to a single contact" of the plurality of image sensor units, patent claim 1 does recite that “each of the plurality of openings enables access to at least one image sensor unit of the plurality of image sensor units” as required by pending claim 11.
10. Applicant’s arguments with respect to the rejections of claims 19-20, 24 and 27 under 35 U.S.C. §102(a)(1) over Cho’s Fig. 13 Embodiment, filed 30 July 2026, have been fully considered but they are not persuasive. With respect to applicant’ argument that Cho does not disclose a unit controller that instructs column control circuitry to address specific individual columns to isolate selected pixel readout signal, it is pointed out that Cho discloses a unit controller CC1/CC2 (para [53-57]), wherein the unit controller (CC1/CC2) is configured to specify selective readout of one or more pixel readout signals by instructing the column control circuitry to address a group of specific columns (which meets the claim limitation “one or more specific columns”) of the array (Cho, para [53-57]; specifically, para [53]: circuit blocks CC1 and CC2 …for selectively routing signals, para [56]: CC2 may be used to map lines such as lines 72 to a selected subset of output lines 40 (wherein the selected output lines 40 are vertical column lines (see Fig. 13), i.e. “to address one or more specific columns”)).
Allowable Subject Matter
11. Claims 16-18, in the absence of a terminal disclaimer, and claims 22 and 32-35 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious a flat panel image sensor, and image sensor unit and a large area flat panel image sensor with all exclusive limitations as recited in claims 16, 17, 22 and 32, which may be characterized (claim 16) in that the plurality of chips are attached to the substrate such that a chip contact of each of the plurality of image sensor units is accessible through at least one of the plurality openings, (claim 17) the PCB includes a plurality of through-holes, the flat panel image sensor further comprising underfill that has been injected into at least one of the through-holes to provide additional structural support for the flat panel image sensor, and at least one of the through-holes is reserved for venting out air during the process of underfilling, (claim 22) in that the image sensor unit has at least two signal amplifiers, the image sensor unit further comprising an analog multiplexor in communication with the unit controller and configured to receive pixel readout signals from one or more pixels and generate a multiplexed readout signal, wherein the unit controller is configured to specify one or more of the pixel read out signals to send to the analog multiplexor from which the multiplexed readout signal is generated, and one or more signal amplifiers to receive the multiplexed readout signal from the analog multiplexor, and (claim 32) in a structured substrate that includes a plurality of openings, and in that the plurality of chips are attached to the substrate such that a chip contact of each of the plurality of image sensor units is accessible through at least one of the plurality openings.
Conclusion
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
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08-25-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818
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