DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Invention I (Claims 1-4, 8-10) in the reply filed on 3/6/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 5-7, 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/6/2026.
Priority
Acknowledgment is made of applicant’s claim for priority under 35 U.S.C. 119 (e).
Drawings
The originally filed drawings were received on 3/25/2024. These drawings are acceptable.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because of the following informalities:
Abstract, line 11- ‘or o beam combiner’ should read ‘or a beam combiner’.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 3-4 are objected to because of the following informalities:
Claim 3, line 1- ‘where in’ should read ‘wherein’.
Claim 4, line 1- ‘where in’ should read ‘wherein’.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 8-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, line 4 recites ‘a significant’. This appears to be incorrect, as a floating point number has a significand, a base, and an exponent. For purposes of examination, this limitation has been taken to be ‘a significand’.
Claim 1, line 9 recites ‘a significant’. This appears to be incorrect, as a floating point number has a significand, a base, and an exponent. For purposes of examination, this limitation has been taken to be ‘a significand’.
Claims 2-4 are dependent on Claim 1, and hence inherit the deficiencies of Claim 1.
Claim 2, line 5 recites ‘a significant’. This appears to be incorrect, as a floating point number has a significand, a base, and an exponent. For purposes of examination, this limitation has been taken to be ‘a significand’.
Claim 8, line 5 recites ‘a significant’. This appears to be incorrect, as a floating point number has a significand, a base, and an exponent. For purposes of examination, this limitation has been taken to be ‘a significand’.
Claim 8, line 10 recites ‘a significant’. This appears to be incorrect, as a floating point number has a significand, a base, and an exponent. For purposes of examination, this limitation has been taken to be ‘a significand’.
Claim 8, line 29 recites the limitation ‘a first stage and a second stage’. However, Claim 8, line 14 also recites the limitation ‘a first stage and a second stage’. This appears to be problematic, since it is not clear whether the stages in line 29 are to refer to those in line 14, or to separate, unique stages not previously recited. For purposes of examination, the limitations in line 29 are interpreted as ‘a third stage and a fourth stage’.
Claim 8, line 20 recites ‘a significant’. This appears to be incorrect, as a floating point number has a significand, a base, and an exponent. For purposes of examination, this limitation has been taken to be ‘a significand’.
Claim 8, line 25 recites ‘a significant’. This appears to be incorrect, as a floating point number has a significand, a base, and an exponent. For purposes of examination, this limitation has been taken to be ‘a significand’.
Claims 9-10 are dependent on Claim 8, and hence inherit the deficiencies of Claim 8.
Allowable Subject Matter
Claims 1, 8 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claims 2-4, 9-10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 1 is allowable over the cited art of record for at least the reason that the cited art of record fails to teach or reasonably suggest a floating point number multiplication unit as generally set forth in Claim 1, the unit including, in combination with the features recited in Claim 1, a first wave modulator that receives a first signal representing an exponent of a first floating point number mapped onto a frequency of a first harmonic wave and a second signal representing a significand of the first floating point number mapped onto an amplitude of the first harmonic wave to produce a first floating point number, representing a first factor in a multiplication; and a second wave modulator that receives a third signal representing an exponent of a second floating point number mapped onto a frequency of a second harmonic wave and a fourth signal representing a significand of the second floating point number mapped onto an amplitude of the second harmonic wave to produce a second floating point number representing a second factor in a multiplication. Claims 2-4 are dependent on Claim 1, and hence are allowable for at least the same reasons Claim 1 is allowable.
Claim 8 is allowable over the cited art of record for at least the reason that the cited art of record fails to teach or reasonably suggest a floating point number vector multiplication unit as generally set forth in Claim 8, the unit including, in combination with the features recited in Claim 8, a first vector for multiplication based on a first wave modulator that receives a first signal representing an exponent of a first floating point number mapped onto a frequency of a first harmonic wave and a second signal representing a significand of the first floating point number mapped onto an amplitude of the first harmonic wave to produce a first floating point number, representing a first factor in a multiplication; a second wave modulator that receives a third signal representing an exponent of a second floating point number mapped onto a frequency of a second harmonic wave and a fourth signal representing a significand of the second floating point number mapped onto an amplitude of the second harmonic wave to produce a second floating point number representing a second factor in a multiplication; and a second vector for multiplication based on a third wave modulator that receives a fifth signal representing an exponent of a third floating point number mapped onto a frequency of a third harmonic wave and a sixth signal representing a significand of the third floating point number mapped onto an amplitude of the third harmonic wave to produce a third floating point number, representing a third factor in a multiplication; a fourth wave modulator that receives a seventh signal representing an exponent of a fourth floating point number mapped onto a frequency of a fourth harmonic wave and a fourth signal representing a significand of the fourth floating point number mapped onto an amplitude of the fourth harmonic wave to produce a fourth floating point number representing a fourth factor in a multiplication. Claims 9-10 are dependent on Claim 8, and hence are allowable for at least the same reasons Claim 8 is allowable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application Publication US 2020/0142441 A1 to Bunandar et al.- Optical processing system that performs matrix multiplications via photonic processor.
TW 202220401A to Bunandar et al.- Photonic processor that can include a dual rail optical multiplier to multiply two numbers, the numbers being represented by voltage values.
U.S. Patent Application Publication US 2017/0293470 A1 to Wang et al.- Floating point multiply-add unit performed in circuitry.
U.S. Patent No. 10481869 to Wang et al.- Floating point fused multiply-add unit performed in optoelectronic circuitry.
WO 2020/103615 A1 to Yan et al.- Photoelectric-based floating point multiplier unit for multiplying two floating point numbers represented as bits in circuitry.
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ARNEL C. LAVARIAS
Primary Examiner
Group Art Unit 2872
3/18/2026
/ARNEL C LAVARIAS/Primary Examiner, Art Unit 2872