DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11, 16 – 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Magni et al. (US 2022/0068741).
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(Claim 11) Magni et al. teach a device, comprising:
a laser direct structure (LDS) material (14) molded onto a semiconductor chip (10) and at least one electrically conductive formation (12b) arranged adjacent the semiconductor chip,
wherein the LDS material has a first thickness (from top surface of #14 to top surface of #12b);
a cavity (top half of #16b) in the LDS material extending from a front surface thereof, the cavity having an end wall between the front surface of the LDS material and the at least one electrically conductive formation,
the LDS material having a second thickness (top half of #16B) at the cavity which is smaller than said first thickness;
at least one via (bottom half of #16B) laser-structured in the LDS material towards the at least one electrically conductive formation (paragraph 88),
where said at least one via laser-structured (bottom half of #16B) in the LDS material is located at the end wall of said cavity, with said at least one via extending between the end wall of said cavity (top half of #16B) and the at least one electrically conductive formation; and
electrically conductive material (16a) in said at least one via laser-structured (bottom half of #16B) in the LDS material to electrically couple a first surface (10b) of the semiconductor chip (10) and the at least one electrically conductive formation (12b).
(Claim 16) Magni et al. teach wherein said semiconductor chip (10) is mounted to a leadframe (12, paragraphs 59, 60) and the at least one electrically conductive formation (12b) is a portion of said leadframe (12).
(Claim 17) Magni et al. teach wherein said cavity (top half of 16b) has a substantially uniform cross-section from the front surface of the LDS material to said end wall.
(Claim 18) Magni et al. teach wherein said cavity (top half of 16b) comprises a trench at the front surface of the LDS material having an elongated end wall with a plurality of vias laser-structured (bottom half of 16b) in the LDS material and the plurality of vias extending between the end wall of said cavity and respective electrically conductive formations (12b).
(Claim 19) Magni et al. teach the device, further comprising encapsulation material (141, paragraph 75) molded into said cavity (16b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Magni et al. (US 2022/0068741) in view of Chiu et al. (US 2017/0148746).
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(Claim 14) Magni et al. lack the device, comprising a stacked (22/20) arrangement of semiconductor chips wherein said semiconductor chip (22) is a first semiconductor chip in the stacked arrangement, and a second semiconductor chip (20) in the stacked arrangement is located under said first semiconductor chip (22).
However, Teh et al. teach a device, comprising a stacked arrangement of semiconductor chips wherein said semiconductor chip is a first semiconductor chip in the stacked arrangement, and a second semiconductor chip in the stacked arrangement is located under said first semiconductor chip for the benefit of increasing the real estate on the substrate (paragraph 50).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of increasing the real estate on the substrate.
(Claim 15) Magni et al. lack wherein said second semiconductor chip provides a substrate.
However, Teh et al. teach wherein said second semiconductor chip (20) provides a substrate for the benefit of increasing the real estate on the substrate (paragraph 50).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of increasing the real estate on the substrate.
Claims 1, 7 – 10 are rejected under 35 U.S.C. 103 as being unpatentable over Magni et al. (US 2022/0068741) in view of Teh et al. (US 2014/0264830).
(Claim 1) Magni et al. teach a method, comprising:
molding laser direct structuring (LDS) material (14) onto a semiconductor chip (10) arranged on a substrate (S), said semiconductor chip having a first surface facing away from the substrate (fig. 6A), and
said substrate having at least one adjacent electrically conductive formation (12b),
wherein the LDS material (14) has a first thickness between a front surface of the LDS material and the substrate;
applying laser beam energy to the LDS material to laser structure therein at least one via (16b) towards the at least one electrically conductive formation, and
electrically coupling (16a) the first surface (10b) of the semiconductor chip and the at least one electrically conductive formation (12) with electrically conductive material in said at least one via laser structured in the LDS material.
Magni et al. lack removing a portion of the LDS material from the front surface to form a cavity in the LDS material having an end wall between the front surface and the at least one electrically conductive formation, the LDS material having a second thickness at the cavity that is smaller than said first thickness;
wherein applying laser beam energy comprises applying laser beam energy to the LDS material at the end wall of said cavity to laser structure therein said at least one via, and
wherein said at least one via extends between the end wall of said cavity and the at least one electrically conductive formation.
However, Teh et al. teach removing a portion of the LDS material (fig. 6 #600/60/610) from the front surface to form a cavity (fig. 6E) in the LDS material having an end wall between the front surface and the at least one electrically conductive formation (604), the LDS material having a second thickness at the cavity that is smaller than said first thickness;
wherein applying laser beam energy comprises applying laser beam energy to the LDS material at the end wall of said cavity to laser structure therein said at least one via (fig. 6F, paragraph 35), and
wherein said at least one via extends between the end wall of said cavity and the at least one electrically conductive formation (figs. 6E – 6G, paragraph 35) for the benefit of improving the interconnect.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of improving the interconnect.
(Claim 7) Magni et al. teach wherein the substrate comprises a portion of a leadframe (paragraph 57).
(Claim 8) Magni et al. lack wherein removing the portion of the LDS material comprises forming the cavity to have a substantially uniform cross-section from the front surface of the LDS material to said end wall.
However, Teh et al teach wherein removing the portion of the LDS material comprises forming the cavity to have a substantially uniform cross-section from the front surface of the LDS material to said end wall (fig. 8) for the benefit of improving the interconnect.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of improving the interconnect.
(Claim 9) Magni et al. lack wherein removing the portion of the LDS material comprise:
forming the cavity as a trench at the front surface of the LDS material having an elongated end wall, and
wherein applying laser beam energy comprises applying laser beam energy to the LDS material at a plurality of locations of said elongated end wall to laser structure therein a plurality of vias extending between the end wall of said cavity and respective electrically conductive formations.
However, Teh et al. teach wherein removing the portion of the LDS material (fig. 6 #600/608/610) comprise:
forming the cavity (fig. 6 #E) as a trench at the front surface of the LDS material having an elongated end wall, and
wherein applying laser beam energy comprises applying laser beam energy to the LDS material at a plurality of locations of said elongated end wall to laser structure therein a plurality of vias extending between the end wall of said cavity and respective electrically conductive formations (paragraph 35) for the benefit of improving the interconnect.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of improving the interconnect.
(Claim 10) Magni et al. teach the method, further comprising, after electrically coupling, molding encapsulation material (fig. 4 #141) into said cavity.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Magni et al. (US 2022/0068741) Teh et al. (US 2014/0264830) in view of Chiu et al. (US 2017/0148746).
(Claim 4) Magni/Teh et al. lack wherein said semiconductor chip is a first semiconductor chip of a stacked arrangement of semiconductor chips including a second semiconductor chip on which said first semiconductor chip is stacked.
However, Teh et al. teach a device, comprising a stacked arrangement of semiconductor chips wherein said semiconductor chip is a first semiconductor chip in the stacked arrangement, and a second semiconductor chip in the stacked arrangement is located under said first semiconductor chip for the benefit of increasing the real estate on the substrate (paragraph 50).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of increasing the real estate on the substrate.
(Claim 5) Magni/Teh et al. lack wherein said substrate is said second semiconductor chip.
However, Teh et al. teach wherein said second semiconductor chip (20) provides a substrate for the benefit of increasing the real estate on the substrate (paragraph 50).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of increasing the real estate on the substrate.
Allowable Subject Matter
Claims 2, 3, 6, 12 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Prior art made of record and not relied upon, considered pertinent to applicant's disclosure are listed in PTO – 892 Form.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272- 1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/IGWE U ANYA/Primary Examiner, Art Unit 2891
May 30, 2026
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