Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1), 102(a)(2) as being anticipated by Han et al. (U. S. Pub. 2011/0187389).
As for claim 1, Han et al. discloses a capacitance measurement device (see the capacitance measurement circuit as shown in Figs. 1, 3 and 6) comprising:
a charging switch (see the switch SW in Fig. 3; and switch SW-UP in Fig. 6) that connects a measurement node (see the node connected to the measurement capacitor Cpad), connected to one-end of a measurement target capacitor (Cpad in Fig. 3), with a power source node (power source node VDD) that applies a first voltage (VDD) in an ON state, and disconnects the measurement node from the power source node (VDD) in an OFF state;
a constant current circuit (see the constant current circuit 51 shown in Fig. 7; also see [0021], [0022] and [0051]) that causes a current of a constant magnitude to flow from the measurement node;
a comparator (see the comparator COMP in Fig. 3 and 6) that compares a voltage of the measurement node (VPAD)with a second voltage (Vref) lower than the first voltage (VDD); and
a processing unit (see the control unit 30 in Fig. 5 and 6) that performs processing to measure a lapse time (using timer 40) from when the charging switch (SW; SW_UP) has changed to the OFF state until an output of the comparator flips (i.e., when OUT flips from high to low in Fig.4; [0013]).
As for claim 2, Han et al. discloses the capacitance measurement device of claim 1, further comprising a discharge switch (see the switch SW in Fig. 1; SW-dn in Fig. 6) connected to the measurement node, the discharge switch discharging charges accumulated in the capacitor (Cpad) in an ON state.
As for claim 3, Han et al. discloses the capacitance measurement device of claim 2, wherein the processing unit (control unit 30 in Fig. 6) controls ON/OFF of the charging switch (SW-UP) and the discharge switch (SW_dn).
As for claim 4, Han et al. discloses the capacitance measurement device of claim 1, wherein the lapse time is a count value of a counter from when the charging switch has changed to the OFF state until the output of the comparator flips (see Fig. 4; [0013]).
As for claim 5, Han et al. discloses the capacitance measurement device of claim 4, further comprising a memory (memory means of the control unit 30 for storing the count value) that records the count value.
As for claim 6, Han et al. discloses the capacitance measurement device of claim 4, wherein the processing unit (control unit 30) computes the capacitance of the capacitor based on the count value (i.e., the value of the capacitance is measured based on the value measured by the timer, see [0012], [0013]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (U. S. Pub. 2011/0187389).
As for claim 7, Han et al. discloses a capacitance measurement device (see the capacitance measurement circuit as shown in Figs. 1, 3 and 6) comprising:
a first charging switch (see the switch SW in Fig. 3; and switch SW-UP in Fig. 6) that connects a measurement node (see the node connected to the measurement capacitor Cpad), connected to one-end of a measurement target capacitor (Cpad in Fig. 3), with a power source node (power source node VDD) that applies a first voltage (VDD) in an ON state, and disconnects the measurement node from the power source node (VDD) in an OFF state;
a first constant current circuit (see the constant current circuit 51 shown in Fig. 7; also see [0021], [0022] and [0051]) that causes a current of a constant magnitude to flow from the first measurement node;
a first comparator (see the comparator COMP in Fig. 3 and 6) that compares a voltage of the first measurement node (VPAD)with a second voltage (Vref) lower than the first voltage (VDD); and
a processing unit (see the control unit 30 in Fig. 5 and 6) that performs processing to measure a lapse time (using timer 40) from when the first charging switch (SW; SW_UP) has changed to the OFF state until an output of the first comparator flips (i.e., when OUT flips from high to low in Fig.4; [0013]).
Still referring to claim 7, Han et al. does not specifically disclose: a second charging switch that connects a second measurement node, connected to an other-end of the capacitor, and the power source node in an ON state, and disconnects the second measurement node and the power source node in an OFF state; a second constant current circuit that causes a current of a constant magnitude to flow
from the second measurement node; a second comparator that compares a voltage of the second measurement node with the second voltage; and wherein the processing unit measure a lapse time from when the second charging switch has changed to the OFF state until an output of the second comparator flips.
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Han et al., to disclose using a duplicated second charging switch, a duplicated second constant current circuit, a duplicated second comparator, so that the processing unit measure a second lapse time as claimed, for the purpose of measuring differential capacitances at a second measurement node of the capacitor connected to the other end of the capacitor, by using the capacitance measurement circuit of Han with constant current circuit for improving signal to noise ratio and minimizing influence of external environment (see [0021], [0022]).
Conclusion
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/AMY HE/Primary Examiner, Art Unit 2858