The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination in this application (18/615,697) filed on March 25, 2024.
The Examiner cites particular sections in the references as applied to the claims below for the convenience of the applicant(s). Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant(s) fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claims 1-20 are pending for consideration.
Drawings
The drawings submitted on March 25, 2024 have been considered and accepted.
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on 9/29/2024 and 5/29/2025. U.S. patents and Foreign Patents have been considered.
Claim Rejections - 35 U.S.C. 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 20 are rejected under 35 U.S.C. 112 (b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as claims recite “an actual pattern”, “an expected pattern”, and “optimal read voltage”, rejected under 35 U.S.C 112(b) as these are relative terms that were not defined in the claims. Further, claims recite "in response to" but don't positively recite that the actions they are responding to occur, where it is unclear if these actions are executed first before the responses to such actions took place.
Claim 2 recites "in response to" but don't positively recite that the actions they are responding to occur, where it is unclear if these actions are executed first before the responses to such actions took place.
Claim 3 recites “an actual ratio”, rejected under 35 U.S.C 112(b) as these are relative terms that were not defined in the claims.
Claim 4 recites "in response to" but don't positively recite that the actions they are responding to occur, where it is unclear if these actions are executed first before the responses to such actions took place. Claim further recites “the expected ratio”, “the actual ratio”, where there is an insufficient antecedent basis for these limitations and also these are relative terms that were not defined in the claims.
Claim 5 recites "in response to" but don't positively recite that the actions they are responding to occur, where it is unclear if these actions are executed first before the responses to such actions took place. Claim further recites “an expected ratio”, “an actual ratio”, where it is unclear if these are different ratios from claim 4 or the same.
Claims 6, 10, 15 and 16 recite "in response to" but don't positively recite that the actions they are responding to occur, where it is unclear if these actions are executed first before the responses to such actions took place.
Claims 7 and 12 recite “bit count”, where it is unclear if this is a different bit count from claim 1 or the same.
Claim 11 recites "in response to" but don't positively recite that the actions they are responding to occur, where it is unclear if these actions are executed first before the responses to such actions took place. Claim further recites “all the optimal read voltage”, where there is an insufficient antecedent basis for these limitations and also these are relative terms that were not defined in the claims; it is also unclear what all the optimal read voltages refer to exactly.
All dependent claims are rejected as having the same deficiencies as the claims they depend from.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 10 and 17-20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by McNeil et al. (US PGPUB 2023/0176741) (hereinafter ‘McNeil’).
As per independent claim 1, McNeil discloses a method of operating a memory system, comprising: performing a first read operation with a first read voltage of a first single read level [(Paragraphs 0017-0018 and 0020-0024; FIGs 1, 3A and 5-6) where McNeil teaches utilizing memory device-originated bit count information for validating read voltage levels. The bit count information can reflect the number of bits having their respective threshold voltages below and/or above each read level that has been utilized in a read strobe. “Read strobe” herein refers to applying a read level voltage to a chosen wordline on order to identify the memory cells having their respective threshold voltages below and/or above the applied read level. Thus, a read operation may include one or more read strobes. A memory device operating in accordance with aspects of the present disclosure is capable of returning, in response to a read strobe, the number of memory cells having their respective threshold voltage values below and/or above the applied read level to correspond to the claimed limitation]; determining an actual pattern of bit count under the first read voltage of the first single read level [(Paragraphs 0017-0018 and 0020-0024; FIGs 1, 3A and 5-6) where Lee teaches upon performing a read strobe, a bit count is returned by the memory devices to the memory sub-system controller or used by the local media controller in order to determine whether the read operation utilizes the read level corresponding to the correct voltage distribution valley. Such determination may involve comparing the actual bit count to the expected bit count, which corresponds to the expected position of the read level with respect to the threshold voltage distributions. Should a significant mismatch between the actual and the expected bit count be detected, the read level can be adjusted in order to compensate for the voltage distribution shift that presumably has caused the actual bit count to deviate from the expected bit count. The sign of the read level adjustment can match the sign of the difference between the expected and the actual bit count: if the actual count of bits having their respective threshold voltages below the applied read level exceeds the expected bit count, the read level should be decreased (i.e., shifted to the left), and vice versa. The adjusted read level can then be utilized for performing subsequent read operations with respect to the wordline to which the initial read strobe has been applied and/or to one or more neighboring wordlines of that wordline to correspond to the claimed limitation]; and in response to that a difference between an expected pattern of bit count and the actual pattern of bit count under the first read voltage of the first single read level is equal to or lower than a first threshold, determining that the first read voltage is a first optimal read voltage [(Paragraphs 0017-0018, 0020-0024, 0046 and 0074-0078; FIGs 1, 3A and 5-6) where McNeil teaches responsive to determining that the difference between the actual and expected bit counts exceeds a predetermined threshold value, the memory sub-system controller 115 can adjust the read voltage accordingly, in order to compensate for the voltage distribution shift that presumably has caused the actual bit count to deviate from the expected bit count. The sign of the read level adjustment can match the sign of the difference between the expected and the actual bit count: if the actual count of bits found to the left of the read level exceeds the expected bit count, the read level should be decreased, and vice versa. In some implementations, the absolute value of read voltage adjustment can reflect the absolute value of the difference between the actual and the expected bit count. In the illustrative example of FIG. 5, the memory sub-system controller can decrease the read level by the value of V.sub.diff before repeating the read operation. In an illustrative example the voltage adjustment V.sub.diff can be proportional to the difference of the actual and expected bit counts; the expected bit count information can be stored in a reserved area of the memory devices 130 (e.g., in the flag byte, which is a reserved area associated with a memory page). During a read operation, the local media controller can compare the stored expected bit count to the actual bit count in order to identify possible significant deviations. Should the difference between the actual and expected bit counts fall below the predetermined threshold value, the memory sub-system controller 115 can continue with the read operation, e.g., issue the next read strobe to the memory device 130 to correspond to the claimed limitation], wherein the first single read level of a first page is under a multi-level architecture [(Paragraphs 0034 and 0066; FIGs 1, 3A and 5-6) where McNeil teaches FIG. 5 schematically illustrates example threshold voltage distributions in a MLC memory page, in accordance with aspects of the present disclosure. Each memory cell can be programmed into four charge states that differ by the amount of charge stored by the cell. FIG. 5 shows example distributions 510A-510D of threshold voltages P(V.sub.T, Q.sub.k) for different MLC charge states, which are separated by valley margins 520A-520C to correspond to the claimed limitation].
As per claim 2, McNeil discloses wherein in response to that the difference between the expected pattern of bit count and the actual pattern of bit count under the first read voltage of the first single read level is higher than the first threshold, determining that the first read voltage is not the first optimal read voltage [(Paragraphs 0017-0018, 0020-0024, 0046 and 0074-0078; FIGs 1, 3A and 5-6) where McNeil teaches responsive to determining that the difference between the actual and expected bit counts exceeds a predetermined threshold value, the memory sub-system controller 115 can adjust the read voltage accordingly, in order to compensate for the voltage distribution shift that presumably has caused the actual bit count to deviate from the expected bit count. The sign of the read level adjustment can match the sign of the difference between the expected and the actual bit count: if the actual count of bits found to the left of the read level exceeds the expected bit count, the read level should be decreased, and vice versa. In some implementations, the absolute value of read voltage adjustment can reflect the absolute value of the difference between the actual and the expected bit count. In the illustrative example of FIG. 5, the memory sub-system controller can decrease the read level by the value of V.sub.diff before repeating the read operation. In an illustrative example the voltage adjustment V.sub.diff can be proportional to the difference of the actual and expected bit counts; the expected bit count information can be stored in a reserved area of the memory devices 130 (e.g., in the flag byte, which is a reserved area associated with a memory page). During a read operation, the local media controller can compare the stored expected bit count to the actual bit count in order to identify possible significant deviations. Should the difference between the actual and expected bit counts fall below the predetermined threshold value, the memory sub-system controller 115 can continue with the read operation, e.g., issue the next read strobe to the memory device 130 to correspond to the claimed limitation].
As per claim 10, McNeil discloses wherein in response to determining that the first read voltage is the first optimal read voltage, the method further comprises: determining a second voltage of a second single read level [(Paragraphs 0017-0018, 0020-0024, 0046, 0074-0078 and 0082; FIGs 1, 3A and 5-6) where McNeil teaches wherein when the difference between the actual and expected bit counts fall below the predetermined threshold value, the memory sub-system controller 115 can continue with the read operation, e.g., issue the next read strobe to the memory device 130; the controller receives, via the memory interface, an actual bit count reflecting the number of memory cells that have their respective threshold voltages below the applied read level voltage. In various implementations, the bit count can be equal to the number of memory cells that have their respective threshold voltages below the applied read level voltage or the number of memory cells that have their respective threshold voltages above the applied read level voltage. In some implementations, the bit count can be represented by the number of memory cells, as described in more detail herein above to correspond to the claimed limitation].
As per claim 17, McNeil discloses determining all optimal read voltages; and performing a normal-read operation based on all the optimal read voltages to read out data [(Paragraphs 0017-0018, 0020-0024, 0046, 0074-0078 and 0082; FIGs 1, 3A and 5-6) where McNeil teaches wherein if the actual count of bits having their respective threshold voltages below the applied read level exceeds the expected bit count, the read level should be decreased (i.e., shifted to the left), and vice versa. The adjusted read level can then be utilized for performing subsequent read operations with respect to the wordline to which the initial read strobe has been applied and/or to one or more neighboring wordlines of that wordline; the controller receives, via the memory interface, an actual bit count reflecting the number of memory cells that have their respective threshold voltages below the applied read level voltage. In various implementations, the bit count can be equal to the number of memory cells that have their respective threshold voltages below the applied read level voltage or the number of memory cells that have their respective threshold voltages above the applied read level voltage. In some implementations, the bit count can be represented by the number of memory cells, as described in more detail herein above to correspond to the claimed limitation].
As per independent claim 18, McNeil discloses a memory device, comprising: a memory cell array comprising memory cells; and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured to: apply a first read voltage of a first single read level to target memory cells in a first read operation [(Paragraphs 0017-0018 and 0020-0024; FIGs 1, 3A and 5-6) where McNeil teaches utilizing memory device-originated bit count information for validating read voltage levels. The bit count information can reflect the number of bits having their respective threshold voltages below and/or above each read level that has been utilized in a read strobe. “Read strobe” herein refers to applying a read level voltage to a chosen wordline on order to identify the memory cells having their respective threshold voltages below and/or above the applied read level. Thus, a read operation may include one or more read strobes. A memory device operating in accordance with aspects of the present disclosure is capable of returning, in response to a read strobe, the number of memory cells having their respective threshold voltage values below and/or above the applied read level to correspond to the claimed limitation]; apply a first shift-read voltage of the first single read level to the target memory cells in a first shift-read operation [(Paragraphs 0017-0018 and 0020-0024; FIGs 1, 3A and 5-6) where Lee teaches upon performing a read strobe, a bit count is returned by the memory devices to the memory sub-system controller or used by the local media controller in order to determine whether the read operation utilizes the read level corresponding to the correct voltage distribution valley. Such determination may involve comparing the actual bit count to the expected bit count, which corresponds to the expected position of the read level with respect to the threshold voltage distributions. Should a significant mismatch between the actual and the expected bit count be detected, the read level can be adjusted in order to compensate for the voltage distribution shift that presumably has caused the actual bit count to deviate from the expected bit count. The sign of the read level adjustment can match the sign of the difference between the expected and the actual bit count: if the actual count of bits having their respective threshold voltages below the applied read level exceeds the expected bit count, the read level should be decreased (i.e., shifted to the left), and vice versa. The adjusted read level can then be utilized for performing subsequent read operations with respect to the wordline to which the initial read strobe has been applied and/or to one or more neighboring wordlines of that wordline to correspond to the claimed limitation]; wherein the first shift-read voltage is determined based on bit count under the first read voltage of the first single read level [(Paragraphs 0017-0018, 0020-0024, 0046 and 0074-0078; FIGs 1, 3A and 5-6) where McNeil teaches responsive to determining that the difference between the actual and expected bit counts exceeds a predetermined threshold value, the memory sub-system controller 115 can adjust the read voltage accordingly, in order to compensate for the voltage distribution shift that presumably has caused the actual bit count to deviate from the expected bit count. The sign of the read level adjustment can match the sign of the difference between the expected and the actual bit count: if the actual count of bits found to the left of the read level exceeds the expected bit count, the read level should be decreased, and vice versa. In some implementations, the absolute value of read voltage adjustment can reflect the absolute value of the difference between the actual and the expected bit count. In the illustrative example of FIG. 5, the memory sub-system controller can decrease the read level by the value of V.sub.diff before repeating the read operation. In an illustrative example the voltage adjustment V.sub.diff can be proportional to the difference of the actual and expected bit counts; the expected bit count information can be stored in a reserved area of the memory devices 130 (e.g., in the flag byte, which is a reserved area associated with a memory page). During a read operation, the local media controller can compare the stored expected bit count to the actual bit count in order to identify possible significant deviations. Should the difference between the actual and expected bit counts fall below the predetermined threshold value, the memory sub-system controller 115 can continue with the read operation, e.g., issue the next read strobe to the memory device 130 to correspond to the claimed limitation].
As per claim 19, McNeil discloses wherein the peripheral circuit is further configured to: store the bit count in a page buffer of the peripheral circuit or the memory cell array [(Paragraphs 0017-0018, 0020-0024, 0046-0048, 0053, 0074-0078 and 0082; FIGs 1, 3A and 5-6) where McNeil teaches wherein upon performing a read strobe, a bit count is returned by the memory devices to the memory sub-system controller or used by the local media controller in order to determine whether the read operation utilizes the read level corresponding to the correct voltage distribution valley; cache register 118 and/or the data register 121 may form (e.g., may form a portion of) a page buffer of the memory device 130; the expected bit count information can be stored in a reserved area of the memory device 130 (e.g., in the flag byte associated with a memory page) and during a read operation can be compared, by the local media controller, to the actual distribution count .A page buffer may further include sensing devices (not shown in FIG. 2) to sense a data state of a memory cell of the array of memory cells 204, e.g., by sensing a state of a data line connected to that memory cell to correspond to the claimed limitation].
As for independent claim 20, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 7-9 are rejected under 35 U.S.C. 103(a) as being unpatentable over McNeil, as applied to claim 1 above, in view of Gautam et al. (US 11,004,525) (hereinafter ‘Gautam’).
As per claim 3, McNeil discloses the method of claim 1.
McNeil does not appear to explicitly disclose wherein the expected pattern comprises an expected ratio of bit count, and the actual pattern comprises an actual ratio of bit count.
However, Gautam discloses wherein the expected pattern comprises an expected ratio of bit count, and the actual pattern comprises an actual ratio of bit count [(Column 2, lines 60-67, Column 3, lines 1-11 and Column 25, lines 50-61) where Gautam teaches a first bit count may correspond with the number of memory cells within a particular threshold voltage distribution with threshold voltages between a first verify level (e.g., 1.7V) and a second verify level (e.g., 1.9V) greater than the first verify level. A second bit count may correspond with the number of memory cells within the particular threshold voltage distribution with threshold voltages greater than the second verify level. A bit count ratio may comprise the second bit count divided by the sum of the first bit count and the second bit count. In one example, if the bit count ratio is between 0.02 and 0.05, then the reduction in the programming voltage may be 100 mV; if the bit count ratio is between 0.05 and 0.10, then the reduction in the programming voltage may be 200 mV; determining a first bit count ratio for a first threshold voltage distribution in response to detection that the memory block has exceeded the first program/erase cycle threshold, determining a first programming voltage adjustment for a programming voltage to be applied to a set of memory cells within the memory block based on the first bit count ratio and the total number of program/erase cycles for the memory block, reducing the programming voltage by the first programming voltage adjustment, and programming the set of memory cells within the memory block using the reduced programming voltage to correspond to the claimed limitation].
McNeil and Gautam are analogous art because they are from the same field of endeavor of data storage management.
At the time of the invention, it would have been obvious to one of ordinary skill in the art, having the teachings of McNeil and Gautam before him or her, to modify the method of McNeil to include the bit count ratios of Gautam because it will enhance system performance.
The motivation for doing so would be [“benefit of adaptively reducing the programming voltage applied to non-volatile memory cells over time as the number of program/erase cycles increases is that memory cell over programming may be minimized which may allow maintenance of a lower read voltage margin at a higher number of endurance cycles. Moreover, the ability to use a lower read voltage may lead to reduced power consumption during read operations” (Column 3, lines 40-50 by Gautam)].
Therefore, it would have been obvious to combine McNeil and Gautam to obtain the invention as specified in the instant claim.
As per claim 7, McNeil discloses wherein after performing the first read operation with the first read voltage of the first single read level, the method further comprises: counting bit count under the first read voltage of the first single read level [(Paragraphs 0017-0018, 0020-0024, 0046, 0074-0078 and 0082; FIGs 1, 3A and 5-6) where McNeil teaches where the bit count information can reflect the number of bits having their respective threshold voltages below and/or above each read level that has been utilized in a read strobe. “Read strobe” herein refers to applying a read level voltage to a chosen wordline on order to identify the memory cells having their respective threshold voltages below and/or above the applied read level. Thus, a read operation may include one or more read strobes. A memory device operating in accordance with aspects of the present disclosure is capable of returning, in response to a read strobe, the number of memory cells having their respective threshold voltage values below and/or above the applied read level; upon performing a read strobe, a bit count is returned by the memory devices to the memory sub-system controller or used by the local media controller in order to determine whether the read operation utilizes the read level corresponding to the correct voltage distribution valley. Such determination may involve comparing the actual bit count to the expected bit count, which corresponds to the expected position of the read level with respect to the threshold voltage distributions. The adjusted read level can then be utilized for performing subsequent read operations with respect to the wordline to which the initial read strobe has been applied and/or to one or more neighboring wordlines of that wordline to correspond to the claimed limitation].
As per claim 8, McNeil discloses wherein counting bit count under the first read voltage of the first single read level further comprises: counting bit count of target memory cells, all the memory cells in a target page, memory cells in one or more pages including the target page, or all the memory cells in all the pages [(Paragraphs 0017-0018, 0020-0024, 0046, 0074-0078 and 0082; FIGs 1, 3A and 5-6) where McNeil teaches where the bit count information can reflect the number of bits having their respective threshold voltages below and/or above each read level that has been utilized in a read strobe. “Read strobe” herein refers to applying a read level voltage to a chosen wordline on order to identify the memory cells having their respective threshold voltages below and/or above the applied read level. Thus, a read operation may include one or more read strobes. A memory device operating in accordance with aspects of the present disclosure is capable of returning, in response to a read strobe, the number of memory cells having their respective threshold voltage values below and/or above the applied read level; upon performing a read strobe, a bit count is returned by the memory devices to the memory sub-system controller or used by the local media controller in order to determine whether the read operation utilizes the read level corresponding to the correct voltage distribution valley. Such determination may involve comparing the actual bit count to the expected bit count, which corresponds to the expected position of the read level with respect to the threshold voltage distributions. The adjusted read level can then be utilized for performing subsequent read operations with respect to the wordline to which the initial read strobe has been applied and/or to one or more neighboring wordlines of that wordline to correspond to the claimed limitation].
As per claim 9, Gautam discloses wherein determining actual pattern of bit count under the first read voltage of the first single read level further comprises: calculating a ratio of a first actual bit count to a second actual bit count to determine the actual ratio of bit count, and wherein determining expected ratio of bit count of each read levels for the first page comprises: calculating a ratio of a first expected bit count to a second expected bit count to determine the expected ratio of bit count [(Column 2, lines 60-67, Column 3, lines 1-11 and Column 25, lines 50-61) where Gautam teaches a first bit count may correspond with the number of memory cells within a particular threshold voltage distribution with threshold voltages between a first verify level (e.g., 1.7V) and a second verify level (e.g., 1.9V) greater than the first verify level. A second bit count may correspond with the number of memory cells within the particular threshold voltage distribution with threshold voltages greater than the second verify level. A bit count ratio may comprise the second bit count divided by the sum of the first bit count and the second bit count. In one example, if the bit count ratio is between 0.02 and 0.05, then the reduction in the programming voltage may be 100 mV; if the bit count ratio is between 0.05 and 0.10, then the reduction in the programming voltage may be 200 mV; determining a first bit count ratio for a first threshold voltage distribution in response to detection that the memory block has exceeded the first program/erase cycle threshold, determining a first programming voltage adjustment for a programming voltage to be applied to a set of memory cells within the memory block based on the first bit count ratio and the total number of program/erase cycles for the memory block, reducing the programming voltage by the first programming voltage adjustment, and programming the set of memory cells within the memory block using the reduced programming voltage to correspond to the claimed limitation].
a(2) CLAIMS ALLOWED IN THE APPLICATION
Per the instant office action, claims 4-6 and 11-16, but would be allowable if rewritten in an independent form and overcome 112 rejections.
The reasons for allowance of claim 4 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein in response to determining that the first read voltage is not the first optimal read voltage, the method further comprises: performing a first shift-read operation with a first shift-read voltage of the first single read level, wherein the first shift-read voltage is determined based on a comparison between the expected ratio of bit count and the actual ratio of bit count under the first read voltage of the first single read level”.
The reason for allowance of claim 11 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein in response to determining all the optimal read voltages, the method further comprises: performing a normal-read operation based on all the optimal read voltages, wherein the normal-read operation is not a first read operation”.
The reason for allowance of claim 12 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “performing a first pre-read operation with a first pre-read voltage; based on a first bit count in the first pre-read operation and a first relationship between bit count and read offset in the first single read level, determining a first read offset; and determining the first read voltage based on the first pre-read voltage and the first read offset”.
Pertinent Prior art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee et al., US PGPUB 2022/0301650– teaches CONTROLLER CONTROLLING SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE CONTROLLER.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jared Ian Rutz whose telephone number is (571)272-5535. The examiner can normally be reached on Monday-Friday, 8:00 AM to 4:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857.
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/MOHAMED M GEBRIL/Primary Examiner, Art Unit 2135
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