Prosecution Insights
Last updated: April 19, 2026
Application No. 18/615,768

SEAMLESS MODE-SWITCH IN DC/DC CONVERTERS

Non-Final OA §103
Filed
Mar 25, 2024
Examiner
CHOI, SEUNG HO
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Infineon Technologies AG
OA Round
1 (Non-Final)
100%
Grant Probability
Favorable
1-2
OA Rounds
2y 7m
To Grant
0%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allow Rate
1 granted / 1 resolved
+32.0% vs TC avg
Minimal -100% lift
Without
With
+-100.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
12 currently pending
Career history
13
Total Applications
across all art units

Statute-Specific Performance

§103
100.0%
+60.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1 resolved cases

Office Action

§103
DETAILED ACTION This Office action is in response to the application filed on 21 March 2024. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Specification The disclosure is objected to because of the following informalities: In paragraph [29], “K1VCSVEK1VEVCSVCSVEVEVCSK1SPWMVEVCSThe switching controller 10 includes” provides an informality. In paragraph [30], “K1VCSVEK1VEVCSVCSVEVEVCSK1SPWMVEVCS - with the reference potential” provides the informality. In paragraph [44], “This function may be linearized to have the following form”, but it does not be linearized. In paragraph [45].[46],[47], and [48], an identified equation is repeated. In paragraph [51], “Accordingly, thee voltage sources are connected in series to provide the voltage”, thee should be three. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-5, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Seong Joong Kim et. al (IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO. 3, pages 814-824; hereafter “Kim”) in view of Chen-Yu Wang et. al (2013 International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), IEEE; DOI: 10.1109/VLDI-DAT.2013.6533804; hereafter “Wang”). -Regarding claim 1; Kim discloses; PNG media_image1.png 598 956 media_image1.png Greyscale A circuit comprising: a converter stage configured to convert an input voltage(Fig. 7; VIN) into an output voltage(Fig. 7; Vo) in accordance with a modulated drive signal (Fig. 7; blue arrow); an error amplifier(Fig. 7; EA) configured to generate an error signal (Fig. 7; VCTRL) representing a difference between the output voltage and a reference voltage (Fig. 7; VREF); a first modulator (Fig. 7; PFM controller) configured to generate a first control signal (Fig. 7; lower red arrow) based on the error signal and a reference signal, a second modulator(Fig. 7; PWM controller) configured to generate a second control signal (Fig. 7; upper red arrow) based on the error signal; a logic circuit (Fig. 7; Mux) configured to provide the drive signal based on the first control signal or the second control signal. Kim discloses techniques to perform automatic and seamless switching between PWM/PFM modes in his paper (IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO. 3, pages 814-824) to maintain high efficiency even in the presence of dynamic load variations. However, Kim does not disclose “the reference signal is controlled dependent on the input voltage and the output voltage”. The reference signal is controlled to match up the duty cycles of two modulators (PFM and PWM). Wang discloses; , wherein the reference signal (Fig. 1; Vsum) is controlled dependent on the input voltage (Fig.1; Vi) and the output voltage (Fig.1; Vo); Wang discloses a high efficiency DC/DC boost regulator with an adaptive off/on time control for the simpler solution of frequency variation and the simpler sensor used. Wang applies the input/output voltages to an adaptive off/on time controller and the output of the controller goes to the reference signal of a comparator (Fig. 1; CMP). Wang teaches and gives a motivation for the input/output voltages into the reference signal in the PFM control in claim 1. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Kim such that a commonly used adaptive on time controller with the input/output voltages described in Wang is applied to the mode switching device for smooth mode transition. Doing so allows for improving the control of multimode switching converter. -Regarding claim 2; Kim discloses: The circuit of claim 1 wherein the error amplifier (Fig. 7; EA) is configured to receive a first signal representing the output voltage (Fig. 7; Vo) and a second signal representing a reference voltage (Fig. 7; VREF), and wherein the error signal (Fig. 7; VCTRL) represents the difference between the first signal and the second signal. -Regarding claim 3; Kim discloses: The circuit of claim 1, wherein the first modulator comprises a pulse-frequency modulator (Fig. 7; PFM Controller) and the first control signal has a pulse frequency that depends on the error signal and the reference signal (Fig. 7; VREF). -Regarding claim 4; Kim discloses: The circuit of claim 3, wherein the second modulator comprises a pulse-width modulator (Fig. 7; PWM Controller) and the second control signal has a specific frequency (Sec. V; CCOs) and a duty cycle (Fig. 7; DPWM) that depends on the error signal (Fig. 7; VCTRL). -Regarding claim 5; Kim discloses: The circuit of claim 1, wherein the logic circuit (Fig. 7; Mux) is configured to output the first control signal or the second control signal as the modulated drive signal (Fig. 7; blue arrow) for the switching stage. For method claim 10, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device “1 inherently performs the claimed process. In re King, 801 F.2d 1324, 231 UPSQ 136 (Fed Cir. 1986). Therefore, the previous rejections based on the apparatus will not be repeated. Allowable Subject Matter Claims 6-9, 11,12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim. The following is a statement of reasons for the indication of allowable subject matter: -with respect to claim 6: the prior arts in Kim, and Wang disclose the claimed invention in basic claims but do not further disclose about a switching circuit dependent on a selection signal. -with respect to claim 7: the prior arts in Kim, and Wang disclose the claimed invention in basic claims but do not further disclose about a further switching circuit dependent on the selection signal. -with respect to claim 8: the prior arts in Kim, and Wang disclose the claimed invention in basic claims but do not further disclose about the selection signal by an external device. -with respect to claim 9: the prior arts in Kim, and Wang disclose the claimed invention in basic claims but do not further disclose about a duty cycle matching between the PWM and the PFM. -with respect to claim 11: the prior arts in Kim, and Wang disclose the claimed invention in basic claims but do not further disclose about a direction of the error signal either to the PWM or the PFM. -with respect to claim 12: the prior arts in Kim, and Wang disclose the claimed invention in basic claims but do not further disclose about a duty cycle matching between the PWM and the PFM by the controlled reference signal of the PFM. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEUNG HO CHOI whose telephone number is (571)272-8188. The examiner can normally be reached Monday-Thursday, 7:30 AM - 5:30 PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached at 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SEUNG HO CHOI/Examiner, Art Unit 2838 /CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838
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Prosecution Timeline

Mar 25, 2024
Application Filed
Jan 23, 2026
Non-Final Rejection — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
100%
Grant Probability
0%
With Interview (-100.0%)
2y 7m
Median Time to Grant
Low
PTA Risk
Based on 1 resolved cases by this examiner. Grant probability derived from career allow rate.

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