DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the higher in-band gain from the virtual RF ground is exhibiting an inherently higher PAE of the differential output signal recited in claim 10, exhibiting a higher amplification stability of the push pull amplifier as measured by the increase of a K-factor stability metric recited in claim 11, stability is requiring less external stabilization of the differential output signal via additional circuitry recited in 12, the increase of the push pull amplification stability is resulting in easier impedance matching between the differential input signal and the differential output signal recited in claim 13, and the increase of the push pull amplification stability is exhibiting higher gain and power added efficiency recited in claim 14 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 6 and 8-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by [Garay et al (Fig. 4B); 11,469,726].
Regarding claims 1 and 8, Garay et al discloses an amplifier circuit comprising a first balun (414), a second balun (420), a first FET (M5) which is coupled to the first balun (414) and the second balun (420), a second FET (M6) which is coupled to the first balun (414) and the second balun (420) and wherein the first FET (M5) and the second FET (M6) are coupled, a first capacitor (the capacitor located between the gate terminal of the first transistor M5 and the drain terminal of the transistor M6) which is coupled to a gate node (gate terminal of M5) of the first FET (M5) and the drain node (drain terminal of M6) of the second FET (M6), and a second capacitor (the capacitor located between the gate terminal of the second transistor M6 and the drain terminal of the first transistor M5) which is coupled to a gate node (gate terminal of M6) of the second FET (M6) and the drain node (drain terminal of M5) of the first FET (M5).
(gate terminal of M5), a drain node (drain terminal of M5), a source node (source terminal of M5), and wherein the first FET (M5) and the second FET (M6) are interconnected (ground) via the source node (the source terminal of M5) of the first FET (M5) and the source node (source terminal of M6) of the second FET (M6).
Regarding claim 2, wherein the first FET (M5) and the second FET (M6) comprise a gate node (gate terminal of M5, gate terminal of M6), a drain node (drain terminal of M5, drain terminal of M6), and a source node (source terminal of M5, source terminal of M6) and wherein the first FET (M5) and the second FET (M6) are interconnected via the source node (source terminal of M5) of the first FET (M5) and the source node (source terminal of M6) of the second FET (M6).
Regarding claim 3, wherein the first capacitor (the capacitor located between the gate terminal of the first transistor M5 and the drain terminal of the transistor M6) is configured to cancel inherent signal feedback between the gate node (gate terminal of M5) and the drain node (drain terminal of M5) of the first FET (M5), and the second capacitor (second capacitor (the capacitor located between the gate terminal of the second transistor M6 and the drain terminal of the first transistor M5) is configured to cancel inherent signal feedback between the gate node (gate terminal of M6) and the drain node (drain terminal of M6) of the second FET (M6).
Regarding claims 4 and 9, Garay et al further comprising a virtual ground (ground connecting to the source terminal of the transistor M5) disposed between the source node (source terminal of the transistor M5) of the first FET (M5) and the source node (source terminal of M6) of the second FET (M6).
Regarding claim 6, wherein an input signal (input signal of M5) of the first FET (M5) is inversely phase balanced an input signal (input signal of M6) of the second FET (M6).
Regarding claims 10-14, the limitations recited in the claims are intended use of the invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over [Garay et al (Fig. 4B); 11,469,726] in view of [Cai et al (Fig. 1); 12,603,615].
Regarding claim 5, Garay et al discloses all the limitations in claim 5 except for that the first input matching network that is coupled to the first balun and the gate node of the first FET and a second IMN that is coupled to the first balun and the gate node of the second FET. Cai et al discloses an amplifier circuit comprising a first input matching network (upper input matching circuit) that is coupled to the power divider and the gate node of the first FET (carrier power amplifier) and a second IMN (lower Input matching circuit) that is coupled to the power divider and the gate node of the second FET (Peak Power amplifier). It would have been obvious to one of ordinary skill in the art at the time the invention was made would have found it obvious to have employed the first input matching network at between the input balun and first FET of Garay et al (Fig. 4B), and second IMN at between the input balun and second FET of Garay et al (Fig. 4B), such as taught by Cai et al (Fig. 1) in order to provide the advantageous benefit of improving the impedance matching for the amplifier circuit.
Regarding claim 7, Garay et al discloses all the limitations in claim 5 except for that the first output matching network that is coupled to the drain node of the first FET and the second balun, and a second OMN that is coupled to the drain node of the second FET and the second balun. Cai et al discloses an amplifier circuit comprising a first output matching network (upper output matching circuit) that is coupled to the drain node of the first FET (carrier power amplifier) and the power combiner, and a second OMN (lower output matching circuit) that is coupled to the drain node of the second FET (Peak Power amplifier) and the power combiner. It would have been obvious to one of ordinary skill in the art at the time the invention was made would have found it obvious to have employed the first output matching network at between the drain node of the first FET and the second balun of Garay et al (Fig. 4B), and second IMN at between the drain node of the second FET and the second balun of Garay et al (Fig. 4B), such as taught by Cai et al (Fig. 1) in order to provide the advantageous benefit of improving the impedance matching for the amplifier circuit.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
7,697,915 teaches a differential amplifier with the cross coupled capacitors.
10,686,474 teaches two transistors with the input balun and output balun.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Choe whose telephone number is (571)272-1760. The examiner can normally be reached MONDAY-FRIDAY 5AM-11:00PM.
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/HENRY CHOE/ Primary Examiner, Art Unit 2843
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