Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the communication filed on 10/29/2025.
The examiner finds the applicant’s amendments sufficient to overcome the teachings of Chen alone. However, new rejections to address the claims as amended have been presented below further in view of Kim and Cayzac.
All objections and rejections not set forth below have been withdrawn.
Claims 1-20 have been examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-12, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US Patent Application Publication Number 2015/0371046) hereinafter referred to as Chen, and further in view of Kim (US Patent Application Publication Number 2005/0268086), and further in view of Cayzac et al. (US Patent Number 4,143,365) hereinafter referred to as Cayzac.
Regarding claim 1, Chen disclosed a method for providing a processor boot architecture with a safety protected memory, the method comprising:
loading computer code in a first memory (Chen Paragraphs 0023, 0026, and 0043-0054 for example – loading the instruction memory startup code);
transmitting an initialization signal corresponding to the computer code in the first memory from the processor to a second memory which has memory protection (Chen Paragraphs 0023, 0026, and 0043-0054 for example – last instruction of the startup code which sends a signal to enables writing to the instruction memory regular runtime code area);
initializing the second memory with the initialization signal, wherein initializing the second memory enables access of the second memory without the memory protection of the second memory raising a fault condition (Chen Paragraphs 0023, 0026, and 0043-0054 for example – latch or the MPU propagating the signal to enable writing to the instruction memory regular runtime code area, which previously was disabled); and
re-enabling memory protection of the first memory (Chen Paragraphs 0023, 0026, and 0043-0054 for example – propagating the signals which disable writing to the instruction memory startup code area or execution of the instructions in the instruction memory startup area).
However, Chen did not explicitly teach in the above context:
providing a memory protection register that is capable of supporting a memory protection disable command (Chen Paragraphs 0023, 0026, and 0043-0054 for example – Chen meets this limitation alone but does not meet it in combination of the remainder of the claim limitations, specifically the newly claimed limitations);
transmitting a memory protection disable command to a processor coupled to the memory protection register (Chen Paragraphs 0023, 0026, and 0043-0054 for example - Chen meets this limitation alone but does not meet it in combination of the remainder of the claim limitations, specifically the newly claimed limitations);
disabling memory protection of a first memory coupled to the processor in response to the memory protection register receiving the memory protection disable command (Chen Paragraphs 0023, 0026, and 0043-0054 for example - Chen meets this limitation alone but does not meet it in combination of the remainder of the claim limitations, specifically the newly claimed limitations);
or that the loading computer code in the first memory occurs after disabling memory protection of the first memory.
Kim taught, in a similar boot up processing system, a protection system including:
providing a memory protection comparator that is capable of supporting a memory protection disable command (Kim Paragraph 0036 for example – where writing the boot code is disabled prior to the comparator indicating that the dummy code matches the reference data – in this case the command is the dummy code);
transmitting a memory protection disable command to a processor coupled to the memory protection comparator (Kim Paragraph 0036 for example – where the comparator indicates a match between the dummy code and the reference data);
disabling memory protection of a first memory coupled to the processor in response to the memory protection comparator receiving the memory protection disable command (Kim Paragraph 0036 for example – where the comparator indicates a match between the dummy code and the reference data thereby allowing loading of the boot code into memory i.e. disabling protection);
or that the loading computer code in the first memory occurs after disabling memory protection of the first memory (Kim Paragraph 0036 for example – where the comparator indicates a match between the dummy code and the reference data thereby allowing loading of the boot code into memory).
It would have been obvious to the person having ordinary skill in the art before the effective filing date of the invention to have employed the teachings of Kim in the boot system of Chen by applying the OTP based control system to prevent premature writing to the startup code memory section. This would have been obvious because the person having ordinary skill in the art would have been motivated to avoid boot operation errors as a result of the power supply not reaching full operating voltage.
Chen and Kim did not teach how the comparison is performed, but did teach storing the reference data in a register.
Cayzac taught a method for comparing data using registers, including two input registers that receive the input data A and B before they are compared. They are applied to the operator which digitally subtracts A and B. Subsequently the result of this subtraction is applied to an electronic switch and the result is applied to a third register, which enables or does not enable the output in accordance with the command which it receives. (See Cayzac Col. 11 Lines 1-13 for example).
It would have been obvious to the person having ordinary skill in the art before the effective filing date of the invention to have employed the teachings of Cayzac in the boot system of Chen and Kim by utilizing comparison circuitry including two registers to compare the dummy data with the reference data. This would have been obvious because the person having ordinary skill in the art would have been motivated to provide a specific means for the generically taught comparing of Chen and Kim.
Regarding claim 10, Chen, Kim, and Cayzac taught the above method of claim 1, including a storage means for enabling memory protection disable command (The register which stores the dummy data prior to comparison in the combination presented above with respect to claim 1), and processor means for disabling protection (The microprocessor or microcontroller which implements the system in the combination presented above with respect to claim 1).
Regarding claim 19, Chen, Kim, and Cayzac taught the above method of claim 1, including a modified memory protection register for enabling memory protection disable command (The register which stores the dummy data prior to comparison in the combination presented above with respect to claim 1), and processor means for disabling protection (The microprocessor or microcontroller which implements the system in the combination presented above with respect to claim 1 – See also Chen Paragraph 0103).
Regarding claim 5, Chen, Kim, and Cayzac taught that the computer code is first computer code, the method further comprising loading second computer code into the first memory if the second computer code is less than or equal to a predetermined size threshold (Chen Paragraphs 0002, 0023, 0026, and 0043-0054 for example).
Regarding claim 6, Chen, Kim, and Cayzac taught that the computer code is first computer code, the method further comprising loading second computer code into the second memory if the second computer code is greater than a predetermined size threshold (Chen Paragraphs 0002, 0023, 0026, and 0043-0054 for example).
Regarding claim 7, Chen, Kim, and Cayzac taught that the first memory, the second memory, and processor are part of a system-on-chip (SoC) (Chen Fig. 4 for example).
Regarding claim 8, Chen, Kim, and Cayzac taught that a test interface controller transmits the memory protection disable command that is part of the computer code to a clock controller which relays the memory protection command to the processor (Chen Paragraphs 0023, 0026, and 0043-0054 – setting and using boot code controlled latches to control the memory protection for example).
Regarding claim 9, Chen, Kim, and Cayzac taught activating a test interface controller mode for the processor and the first memory (Chen Paragraphs 0023, 0026, and 0043-0054 – setting and using boot code controlled latches to control the memory protection for example).
Regarding claim 11, Chen, Kim, and Cayzac taught that the storage means comprises a modified memory protection register for supporting the memory protection disable command (Chen Paragraphs 0023, 0026, and 0043-0054 for example, Kim Paragraph 0036, and Cayzac Col. 11 Lines 1-13 for example).
It would have been obvious to the person having ordinary skill in the art before the effective filing date of the invention to have employed the teachings of Kim in the boot system of Chen by applying the OTP based control system to prevent premature writing to the startup code memory section. This would have been obvious because the person having ordinary skill in the art would have been motivated to avoid boot operation errors as a result of the power supply not reaching full operating voltage.
It would have been obvious to the person having ordinary skill in the art before the effective filing date of the invention to have employed the teachings of Cayzac in the boot system of Chen and Kim by utilizing comparison circuitry including two registers to compare the dummy data with the reference data. This would have been obvious because the person having ordinary skill in the art would have been motivated to provide a specific means for the generically taught comparing of Chen and Kim.
Regarding claim 12, Chen, Kim, and Cayzac taught that the processor means comprises at least one of a central processing unit and a multi-core processor (Chen Paragraphs 0023, 0026, 0035, and 0043-0054 for example).
Regarding claim 16, Chen, Kim, and Cayzac taught that the computer code is first computer code, the system further comprising the first memory being loaded with second computer code if the second computer code is less than a predetermined size threshold (Chen Paragraphs 0002, 0023, 0026, and 0043-0054 for example).
Regarding claim 17, Chen, Kim, and Cayzac taught that the computer code is first computer code, the system further comprising the second memory being loaded with second computer code if the second computer code is greater than a predetermined size threshold (Chen Paragraphs 0002, 0023, 0026, and 0043-0054 for example).
Regarding claim 18, Chen, Kim, and Cayzac taught that the first memory, the second memory, and processor are part of a system-on-chip (SoC) (Chen Fig. 4 for example).
Regarding claim 20, Chen, Kim, and Cayzac taught that the processor comprises at least one of a central processing unit and a multi-core processor (Chen Paragraphs 0023, 0026, 0035, and 0043-0054 for example).
Claims 2-4, and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, Kim, and Cayzac, and further in view of Song et al. (US Patent Application Publication Number 2016/0371012) hereinafter referred to as Song.
Regarding claims 2, 3, 13 and 14, Chen, Kim, and Cayzac did not explicitly teach that the first memory comprises tightly coupled memory (TCM), or that the second memory comprises at least one of static random-access memory (SRAM) and other tightly coupled memory (TCM) (Chen doesn’t appear to explicitly teach or limit the memory to any particular type).
Song taught in a boot processing system that internal memory for storing boot code can be implemented using TCM (Song Paragraph 0034 for example).
IT would have been obvious to the person having ordinary skill in the art before the effective filing date of the invention to have employed the teachings of Song in the memory protection system of Chen, Kim, and Cayzac by implementing the internal memory of Chen using TCM. This would have been obvious because the person having ordinary skill in the art would have been motivated to employ a specific type of memory for the generically taught internal memory of the boot system of Chen.
Regarding claims 4 and 15, Chen, Kim, and Cayzac did not explicitly teach memory protection of the second memory comprises Error-Correcting Code (ECC). However, ECC is well known in memory protection.
Further, Song taught that ECC can be used to protect the internal memory (Song Paragraph 0041 for example).
It would have been obvious to the person having ordinary skill in the art before the effective filing date of the invention to have employed the teachings of Song in the boot memory system of Chen, Kim, and Cayzac by employing ECC to the internal memory. This would have been obvious because the person having ordinary skill in the art would have been motivated to detect and correct errors included in data being written to or read from the memory.
Conclusion
Claims 1-20 have been rejected.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW T HENNING whose telephone number is (571)272-3790. The examiner can normally be reached Monday-Friday 9AM-3PM EST.
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/MATTHEW T HENNING/ Primary Examiner, Art Unit 2491