DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
This action is in reply to the Applicant Response filed on 12/5/2025.
Claims 1 and 10 have been amended and are hereby entered.
Claims 1, 3-4, 7, 10-12, 15 and 18 are currently pending and have been examined.
Applicants Subject Matter Expert Disclosure filed on 3/25/2026 is addressed below as insufficient to overcome eligibility under 101.
This action is made FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 3-4, 7, 10-12, 15 and 18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 1 and 10 recite “said distributed programming platform operable to reduce processing latency to allow realization of intraday volatility windows.” The Examiner rejects this amended claim under 35 U.S.C. 112(a), as the specification as filed on (3/25/2024) was reviewed , and no discussion regarding processing latency could be found; Thus failing to provide written description support for this particular claim limitation.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 3-4, 7, 10-12, 15 and 18 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (abstract idea) without significantly more.
Under the broadest reasonable interpretation, the following claim terms are presumed to have their plain meaning consistent with the specification as it would be interpreted by one of ordinary skill in the art. MPEP § 2111.
Claims 1, 3-4, 7, 10-12, 15 and 18 recite “nodeservice.” Nodeservice is a software component such as VS Code or NuGet, which leverages hardware processor for computation.
Claims 1, 3-4, 7, 10-12, 15 and 18 recite “client.” According to Applicant Specification (Para. 50), “client” includes python code as a software library.
Claims 1, 3-4, 7, 10-12, 15 and 18 recite “scheduler.” A scheduler in a HUF platform is considered an algorithm.
Claims 1, 3-4, 7, 10-12, 15 and 18 recite “tensor core.” A tensor core is a specialized processing unit in an NVIDIA graphic processing unit.
Claims 1, 3-4, 7, 10-12, 15 and 18 recite “system interface of peripheral component,” which is a graphics card or network adaptor.
Step 1: Does the Claim Fall within a Statutory Category? (see MPEP 2106.03)
Claim 1 recites a process, which is a statutory category of invention (Step 1: YES).
Step 2A, Prong One: Is a Judicial Exception Recited? (see MPEP 2106.04(a)). Yes.
The claim is analyzed to determine whether it is directed to a judicial exception. The following claims identify the limitations that recite additional elements in bold and the abstract idea without bold. Underlined claim limitations denote newly added claim limitations:
The claim is analyzed to determine whether it is directed to a judicial exception. Claims 1 recites a method for harvesting intraday volatility by electronically transacting over-the-counter transactions in multiple partitions during a time period, said multiple partitions comprising predetermined windows of time, the method comprising: at a processing grid, the processing grid comprising a plurality of hardware processors, the processing grid operating a distributed programming platform, said distributed programming platform comprising a client, a scheduler and a plurality of nodes, the client, the scheduler and the plurality of nodes operating on the plurality of hardware processors, said distributed programming platform operable to reduce processing latency to allow realization of intraday volatility windows: receiving an observation from an exchange, every one second, within the predetermined windows of time, said predetermined windows of time occurring multiple times in one day, said observation comprising an observation time plus/minus a fixed observation time quantity; and processing the observation received from the exchange, the processing comprising: at the client: serializing a plurality of parameters included in the observation based on the serializing, generating a plurality of task structures comprising: computation of an intraday index value for an index, said intraday index value comprising a time weighted average price ("TWAP"); determination of a market condition for a buyer/seller based on the intraday index value; computation of prices of options on the index; computation of derivatives of the prices; determination of a quantity of one of the over- the-counter transactions to trade; and generating a buy/sell instruction of one of the over-the-counter transactions; and transmitting the plurality of task structures to the scheduler; and receiving a plurality of finalized task structures through an active polling loop that repeatedly queries the scheduler; and at the scheduler: receiving the plurality of task structures; scheduling the plurality of task structures within the distributed programming platform, wherein each node, included in the plurality of nodes, operates a nodeservice, and each nodeservice manages execution of the task structures assigned to the node on which the nodeservice resides; upon execution of the task structures at the plurality of nodes, collecting, from the plurality of nodes, results of the executed plurality of task structures; generating the plurality of finalized task structures from the results of the executed plurality of task structures; and transmitting the plurality of finalized task structures to the client through the active polling loop; and at a trading processor: generating a graphical user interface ("GUI") for a user operating the trading processor, said GUI configured to be refreshed on a per second basis, said refresh based on receiving the finalized task structures from the processing grid on a per second basis, said GUI enabling the user to buy or sell one of the over-the-counter transactions based on the determined market condition, said GUI: displaying: an instrument identifier, a weight, a total delta in percentage and a total delta in currency; and receiving a task instruction to buy or sell one of the over-the-counter transactions; and transmitting, the task instruction to buy or sell one of the over-the-counter transactions to the exchange; wherein each of the plurality of hardware processors comprise the following specifications: not less than 640 tensor cores; not less than 5,120 compute unified device architecture ("CUDA") cores; not less than a double precision performance at between 7 and 8.2 trillion floating point operations per second ("TFLOPS"); not less than a single precision performance at between 14 and 16.4 TFLOPS; not less than a tensor performance at between 112 and 130 TFLOPS; not less than a graphical processing unit ("GPU") memory at between 32 gigabyte ("GB")/16 GB HBM2 ("Second Generation High Bandwidth Memory") and 32 GB HBM2; not less than a memory bandwidth between 900 GB/sec and 1134 GB/sec; not less than an error correction code ("ECC"); not less than an interconnect bandwidth between 32 GB/sec and 300 GB/sec; not less than a system interface of peripheral component interconnect express (PCIe) third generation ("Gen3") and/or a wire-based serial multi-lane near-range communications link ("NVLink"); not less than a form factor of PCIe Full Height/Length or a high bandwidth socket solution ("SXM2"); not less than a maximum power consumption of between 250 W and 300 W; not less than a passive thermal solution; and a plurality of computer application programming interfaces ("APIs") that support CUDA (Compute Unified Device Architecture, running compute kernels on general purpose computing on graphics processing units ("DirectCompute"), a framework for writing programs that execute across heterogenous platforms ("OpenCL") and a programming standard for parallel computing ("OpenACC"). These limitations, as drafted, under its broadest reasonable interpretation, covers performance via certain methods of organizing human activity, but for the recitation of generic computer components. Under human activity, the limitations are a fundamental economic practice, such as hedging or mitigating risk (see Applicants specification, Para. 69, discussing hedging; and Para. 2, discussing hedging risk). Under human activity, the limitations are commercial interactions, such as facilitating a transaction by “generating a buy sell interaction” and facilitates a transaction in a management of a commercial relationship. The mere recitation of generic computer components in the claims do not necessarily preclude that claim from reciting an abstract idea. (Step 2A-Prong 1: Yes. The claims recite an abstract idea).
Step 2A, Prong Two: Is the Abstract Idea Integrated into a Practical Application? (see MPEP 2106.04(d)). No.
The above judicial exception is not integrated into a practical application. In particular, the claim recites the additional elements of processing grid, plurality of hardware processors, distributed programing platform, client, scheduler, plurality of nodes, exchange, nodeservice, tensor cores, unified device architecture (CUDA) cores, graphical processing unit (GPU) memory, memory, system interface of peripheral component interconnect express, wire-based serial multi-lane near-range communication link, plurality of computer application programming interfaces (APIs), CUDA, general purpose computing on graphics processing units, heterogeneous platforms, parallel computing, intraday volatility windows, and graphical user interface. The additional elements of processing grid, plurality of hardware processors, distributed programing platform, client, scheduler, plurality of nodes, exchange, nodeservice, tensor cores, unified device architecture (CUDA) cores, graphical processing unit (GPU) memory, memory, system interface of peripheral component interconnect express, wire-based serial multi-lane near-range communication link, plurality of computer application programming interfaces (APIs), CUDA, general purpose computing on graphics processing units, heterogeneous platforms, parallel computing, are just applying generic computer components to the recited abstract limitations (MPEP 2106.05(f)). The additional elements of a system interface, intraday volatility windows and graphical user interface are generally linking the use of the judicial exception to a particular technological environment or field of use, for the particular technology of Graphical User Interface (MPEP 2106.05(h)). The computer components are recited at such a high-level of generality (i.e. as a generic computer components) such that it amounts to no more than mere instructions to apply the exception using generic computer components, and the claims fail to recite technological detail as to how the step of the judicial exception is accomplished. Accordingly, these additional elements, when considered separately and as an ordered combination, do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea and are at a high level of generality. (Step 2A-Prong 2: NO. The judicial exception is not integrated into a practical application).
Step 2B: Does the Claim Provide an Inventive Concept? (see MPEP 2106.05). No.
The claim is next analyzed to determine if there are additional claim limitations that individually, or as an ordered combination, ensure that the claim amounts to significantly more than the abstract ideas (whether claim provides inventive concept). As discussed with respect to Step 2A2 above, the additional elements of (processing grid, plurality of hardware processors, distributed programing platform, client, scheduler, plurality of nodes, exchange, nodeservice, tensor cores, unified device architecture (CUDA) cores, graphical processing unit (GPU) memory, memory, system interface of peripheral component interconnect express, wire-based serial multi-lane near-range communication link, plurality of computer application programming interfaces (APIs), CUDA, general purpose computing on graphics processing units, heterogeneous platforms, parallel computing, intraday volatility windows, and graphical user interface) in the claims amount to no more than mere instructions to apply the exception using a generic computer component and generally linking the use of GUI’s to judicial exception. The same analysis applies here in Step 2B, i.e., mere instructions to apply an exception using a generic computer component and generally linking the use of GUI’s to judicial exception cannot integrate a judicial exception into a practical application at Step 2A or provide an inventive concept in Step 2B. Viewing the limitations as an ordered combination does not add anything further than looking at the limitations individually. When viewed either individually, or as an ordered combination, the additional limitations do not amount to a claim as a whole that is significantly more than the abstract idea itself. Therefore, the claims do not amount to significantly more than the recited abstract idea (Step 2B: NO; The claims do not provide significantly more, and are not patent eligible).
Claim 3 recites wherein the observation time is at least one of 10:00 AM, 11:00 AM, 12:00 PM, 1:00 PM, 2:00 PM or 3:00 PM. These limitations are also part of the abstract idea identified in claim 1, and is similarly rejected under the same rationale as claim 1, supra.
Claim 4 recites wherein the fixed observation time quantity is two minutes. These limitations are also part of the abstract idea identified in claim 1, and is similarly rejected under the same rationale as claim 1, supra.
Claim 7 recites wherein the TWAP is calculated as an arithmetic average of each tick in the index, between observation times minus two minutes and the observation time. These limitations are also part of the abstract idea identified in claim 1, and is similarly rejected under the same rationale as claim 1, supra.
Claim 10:
Step 1: Does the Claim Fall within a Statutory Category? (see MPEP 2106.03)
Claim 10 recites a system which is a statutory category of invention (Step 1: YES).
Step 2A, Prong One: Is a Judicial Exception Recited? (see MPEP 2106.04(a)). Yes.
The claim is analyzed to determine whether it is directed to a judicial exception. The following claims identify the limitations that recite additional elements in bold and the abstract idea without bold. Underlined claim limitations denote newly added claim limitations:
The claim is analyzed to determine whether it is directed to a judicial exception.
Claim 10 recites a system operating on a hardware processor in combination with a hardware memory for harvesting intraday volatility by electronically transacting over-the-counter transactions in multiple partitions during a time period, said multiple partitions comprising predetermined windows of time, the system comprising: a processing grid comprising: a plurality of processing units; and a distributed programming platform operating on the plurality of processing units, said distributed programming platform operable to reduce processing latency to allow realization of intraday volatility windows, the distributed programming platform comprising: a client; a scheduler; and a plurality of nodes; the processing grid operable to: receive, from an exchange, an observation, every one second, within the predetermined windows of time, said predetermined windows of time occurring multiple times in one day, said observation comprising an observation time plus/minus a fixed observation time quantity; process the observation received from the exchange, the process comprising: the client operable to: serialize a plurality of parameters included in the observation; based on the serialize, generate a plurality of task structures comprising: computation of an intraday index value for an index, the intraday index value comprising a time weighed average price ("TWAP"); determination of a market condition for a buyer/seller based on the intraday index value; computation of prices of options on the index; computation of derivatives of the prices; determination of a quantity of one of the over-the- counter transactions to trade; and generation of a buy/sell instruction of one of the over- the-counter transactions; and transmits the plurality of task structures to the scheduler; and receives a plurality of finalized task structures through an active polling loop that repeatedly queries the scheduler; and the scheduler operable to: receive the plurality of task structures; schedule the plurality of task structures within the distributed programming platform, wherein each node, included in the plurality of nodes, operates a nodeservice, and each nodeservice manages execution of the task structures assigned to the node on which the nodeservice resides; upon execution of the task structures at the plurality of nodes, collects, from the plurality of nodes, results of the executed plurality of task structures; generates the plurality of finalized task structures from the results; and transmits the plurality of finalized task structures to the client through the active polling loop; and a user interface operating at a trader processor, the user interface operable to: receive, at a rate of one second, the finalized task structures from the processing grid; refresh at a rate of one second; an observation display operable to display the observation; display an instrument identifier, a weight, a total delta in percentage, a total delta in currency amount; display an index display operable to display the intraday index value; display a market condition display operable to display the determined market condition; display a buy/sell selection button operable to receive a buy/sell instruction from a user to buy/sell one of the over-the-counter transactions based on the determined market condition; receiving, a task instruction to buy or sell one of the over-the- counter transactions; transmits an electronic instruction to the exchange to buy/sell one of the over-the-counter transactions; wherein each of the two or more processing units comprises: not less than a double precision floating point format ("FP64") of 9.7 trillion floating point operations per second ("TFLOPS"); not less than a double precision tensor cores ("FP64 Tensor Core") of 19.5 TFLOPS; not less than a single precision floating point format ("FP32") of 19.5 TFLOPS; not less than a tensor float 32 ("TF32") of 156 TFLOPS to 312 TFLOPS; not less than a brain floating point ("BFLOAT 16") of 312 TFLOPS to 624 TFLOPS; not less than a half precision floating point format ("FP16") Tensor Core of312 TFLOPS to 624 TFLOPS; not less than a INT8 Tensor Core of 624 tera operations per second ("TOPS") to 1248 TOPS; not less than a graphical processing unit ("GPU") memory of 80GB HBM2e; not less than a GPU memory bandwidth of 1935 GB/s to 2039 GB/s; and not less than a maximum thermal design power of 300 Watt ("W") to 500 W. These limitations, as drafted, under its broadest reasonable interpretation, covers performance via certain methods of organizing human activity, but for the recitation of generic computer components. Under human activity, the limitations are a fundamental economic practice, such as hedging or mitigating risk (see Applicants specification, Para. 69, discussing hedging; and Para. 2, discussing hedging risk). Under human activity, the limitations are commercial interactions, such as facilitating a transaction by “generating a buy sell interaction” and facilitates a transaction in a management of a commercial relationship. The mere recitation of generic computer components in the claims do not necessarily preclude that claim from reciting an abstract idea. (Step 2A-Prong 1: Yes. The claims recite an abstract idea).
Step 2A, Prong Two: Is the Abstract Idea Integrated into a Practical Application? (see MPEP 2106.04(d)). No.
The above judicial exception is not integrated into a practical application. In particular, the claim recites the additional elements of a system, hardware processor, hardware memory, processing grid, processing units, distributed programming platform, client, scheduler, plurality of nodes, exchange, nodeservice observation display, electronic instruction to the exchange, tensor cores, graphical processing unit (GPU) memory, GPU memory, intraday volatility windows, and user interface. The elements of a system, hardware processor, hardware memory, processing grid, processing units, distributed programming platform, client, scheduler, plurality of nodes, exchange, nodeservice observation display, electronic instruction to the exchange, tensor cores, graphical processing unit (GPU) memory, GPU memory are just applying generic computer components to the recited abstract limitations (MPEP 2106.05(f)). The additional elements of intraday volatility windows and user interface are generally linking the use of the judicial exception to a particular technological environment or field of use, for the particular technology of Graphical User Interfaces (MPEP 2106.05(h)). The computer components are recited at such a high-level of generality (i.e. as a generic computer components) such that it amounts to no more than mere instructions to apply the exception using generic computer components, and the claims fail to recite technological detail as to how the step of the judicial exception is accomplished. Accordingly, these additional elements, when considered separately and as an ordered combination, do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea and are at a high level of generality. (Step 2A-Prong 2: NO. The judicial exception is not integrated into a practical application).
Step 2B: Does the Claim Provide an Inventive Concept? (see MPEP 2106.05). No.
The claim is next analyzed to determine if there are additional claim limitations that individually, or as an ordered combination, ensure that the claim amounts to significantly more than the abstract ideas (whether claim provides inventive concept). As discussed with respect to Step 2A2 above, the additional elements of (a system, hardware processor, hardware memory, processing grid, processing units, distributed programming platform, client, scheduler, plurality of nodes, exchange, nodeservice observation display, electronic instruction to the exchange, tensor cores, graphical processing unit (GPU) memory, GPU memory, intraday volatility windows, and user interface) in the claims amount to no more than mere instructions to apply the exception using a generic computer component and generally linking the use of GUI’s to judicial exception. The same analysis applies here in Step 2B, i.e., mere instructions to apply an exception using a generic computer component and generally linking the use of GUI’s to judicial exception cannot integrate a judicial exception into a practical application at Step 2A or provide an inventive concept in Step 2B. Viewing the limitations as an ordered combination does not add anything further than looking at the limitations individually. When viewed either individually, or as an ordered combination, the additional limitations do not amount to a claim as a whole that is significantly more than the abstract idea itself. Therefore, the claims do not amount to significantly more than the recited abstract idea (Step 2B: NO; The claims do not provide significantly more, and are not patent eligible).
Claim 11 recites wherein the observation time is at least one of 10:00 AM, 11:00 AM, 12:00 PM, 1:00 PM, 2:00 PM or 3:00 PM. These limitations are also part of the abstract idea identified in claim 10, and is similarly rejected under the same rationale as claim 10, supra.
Claim 12 recites wherein the fixed observation time quantity is two minutes. These limitations are also part of the abstract idea identified in claim 10, and is similarly rejected under the same rationale as claim 10, supra.
Claim 15 recites wherein the TWAP is calculated as an arithmetic average of each tick in the index, between observation times minus two minutes and the observation time. These limitations are also part of the abstract idea identified in claim 10, and is similarly rejected under the same rationale as claim 10, supra.
Claim 18 recites wherein the user interface is refreshed at least every one second. These limitations are also part of the abstract idea identified in claim 10, and the additional elements of user interface are generally linking the use of the judicial exception to a particular technological environment or field of use, for the particular technology of computer displays (MPEP 2106.05(h)), and the claim fails to recite technological detail as to how the step of the judicial exception is accomplished. Therefore, this claim is similarly rejected under the same rationale as claim 10, supra.
Affidavit or Declaration Under 37 CFR 1.132: Insufficient
The Declaration under 37 CFR 1.132 filed 3/25/2026 is insufficient to overcome the rejection of claims 1 and 10 based upon 35 U.S.C. 101 as set forth in the last Office action because:
Regarding paragraph 4, Examiner respectfully disagrees, as the originally filed specification (3/25/2024) does not disclose details for reduced processing latency.
Regarding paragraph 6, Applicant hasn’t shown that they invented or improved this hardware processors.
Regarding paragraph 9, Applicant has not shown that the applicant has improved the technology, as computer would inherently reduce latency. Additionally, the specification does not connect any technical improvement to reduced latency. The latency is just the result of using the computing device. It appears that the applicant is still using a programmed general purpose computing device to implement the abstract idea.
In view of the foregoing, when all of the evidence is considered, the totality of the rebuttal evidence insufficient to overcome eligibility under 101.
Response to Arguments
Applicant's arguments filed 3/25/2026 have been fully considered but they are not persuasive.
Applicant argues Mackay for reasons that the currently recited claims overcome the 101 rejection. Examiner disagrees, as Mackay dealt with “a mathematical formula was employed to use standing wave phenomena in an antenna system,” where as the currently recited claims deal with a NDVIA type processor attached to user interface for intraday trading.
Regarding the active polling loop and task transmission to nodes, the focus of the claims is not on such an improvement in computers as tools, but on certain independently abstract ideas that use computers as tools. The claims here are not directed to a specific improvement to computer functionality. Rather, they are directed to the use of conventional or generic technology in a well-known environment, without any claim that the invention reflects an inventive solution to any computer specific problem. More specifically, the claims are limited to a business solution to a technical problem, not a technical solution to a technical problem. Applicant also argues that the claimed subject matter is a non-abstract improvement to computer technology, such as automated document processing. Examiner notes that the focus of the claims is not on such an improvement in computers as tools, but on certain independently abstract ideas that use computers as tools.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON M DUCK whose telephone number is (469)295-9049. The examiner can normally be reached 8am - 5pm.
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/BRANDON M DUCK/Examiner, Art Unit 3693
/ELIZABETH H ROSEN/Primary Examiner, Art Unit 3693
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