DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 02 January 2026 is acknowledged.
Claims 8-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02 January 2026.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10 April 2024, 23 September 2024, 07 November 2024, 23 April 2025 have been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Anderson et al. (US 2017/0348968 – hereinafter Anderson.)
Regarding claim 1,
Anderson discloses an integrated circuit for a fluid ejection device, the integrated circuit comprising:
a data interface [‘Serial Column Data’ in fig. 6; paragraphs 0066-0069];
an output interface [108 / 110 in figs. 1a and 1c; paragraphs 0032-0039 and 0041]; and
a shift register [107a-107n in figs. 1a and 6] to shift nozzle data into the integrated circuit through the data interface and shift the nozzle data out of the integrated circuit through the output interface [paragraphs 0032-0039 and 0066-0069.]
Regarding claim 2,
Anderson further discloses the integrated circuit further comprising:
a configuration register storing data to enable or disable the shifting of the nozzle data out of the integrated circuit through the output interface [paragraphs 0067-0068; necessary for enabling the test mode by the DBD circuit module 104.]
Regarding claim 3,
Anderson further discloses the integrated circuit further comprising:
a fire interface [600 in fig. 6]; and
a delay circuit [109a-109n in fig. 6] to receive a fire signal through the fire interface and output a delayed fire signal through the output interface [paragraphs 0066-0069.]
Regarding claim 4,
Anderson further discloses the integrated circuit further comprising:
a configuration register [115 in fig. 6] storing data to enable or disable the output of the delayed fire signal through the output interface [paragraphs 0032, 0041, 0066, and 0068.]
Regarding claim 5,
Anderson further discloses the integrated circuit further comprising:
an analog circuit [106 in fig. 1a] to output an analog signal to the output interface [paragraphs 0032-0033 and 0041]; and
control logic to activate the analog circuit or the shift register to shift the nozzle data out of the integrated circuit through the output interface [paragraphs 0032-0033 and 0041.]
Regarding claim 5,
Anderson further discloses wherein the data interface comprises a single contact pad, a single pin, a single bump, or a single wire [implicit from fig. 6 that each primitive will have its own single wiring.]
Regarding claim 7,
Anderson further discloses wherein the output interface comprises a single contact pad, a single pin, a single bump, or a single wire [well-known and implicit from figs. 1a and 1c that the test results will be output by a single wiring.]
Communication with the USPTO
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JANNELLE M LEBRON whose telephone number is (571)272-2729. The examiner can normally be reached Monday-Friday: 9:00am - 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Douglas X Rodriguez can be reached at (571) 431-0716. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JANNELLE M LEBRON/Primary Examiner, Art Unit 2853