DETAILED ACTION
Response to Amendment
The Amendment filed April 29, 2026 has been entered. Claims 1-20 remain pending in the application. Applicant's amendments to the claims have overcome the 35 U.S.C. 103 rejections previously set forth in the Non-Final Office Action mailed February 12, 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 16 is objected to because of the following informalities: the claim should recite “the host computing device is in an idle state.” Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 4-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2014/0019677), Boenapalli et al. (US 2025/0103232), Chen et al. (US 2010/0306448), and Hinkle (US 2023/0297236).
Regarding claim 1, Chang et al. disclose:
A persistent memory controller for memory management, the persistent memory controller comprising (FIG. 1 Processor 102 corresponding to FIG. 6 Processor 600) comprising:
metadata controller circuitry configured to generate metadata (Fig. 6 Cache Usage Tracker 630 of Processor 600; [0056] The processor (600) may have a cache usage tracker (630) that tracks the usage of the memory blocks in the cache) based on the metadata controller monitoring data in volatile memory (Fig. 1 Cache 104; [0018] cache (104), for example, may be a memory cache, a processor memory cache, an off-chip memory cache, a random access memory cache, or combinations thereof. The memory cache may contain data, executable code, other information, or combinations thereof. In some examples, the cache uses dynamic random access memory (DRAM), static random access memory (SRAM), another volatile memory) (Fig. 4 metadata 410; [0038] metadata (410) may track usage statistics about each block (404, 406, 408) in the row (402). For example, the metadata (410) may show the times and the frequency that each block is referenced; [0039] The metadata (410) may include information about whether the memory block has information written to it. For example, a "1" stored in a particular metadata field may indicate that information has been written to the memory block. In some examples, when a memory block has been written to or has been changed, the memory block is referred to as a dirty block. The memory device may use these metadata fields to determine which blocks are dirty);
memory manager circuitry (Fig. 6 Processor 600) configured to generate a request to remove the data in the volatile memory based on the metadata ([0040] the metadata fields that indicate that the memory block is dirty may be used when determining which memory blocks to write back to the non-volatile memory); and
data controller circuitry configured to process the request (Fig. 6 Processor 600; Fig. 10 step 1014 Request that dirty blocks are written back to the NVM during a background operation) based on a request criterion (Fig. 10 step 1016 Is processor executing on demand requests?) and the arbitrator circuitry allowing the request to proceed to the data controller circuitry (Fig. 10 step 1018 Write back selected dirty blocks to NVM)…and wherein the request criterion is based on the request generated by the memory manager circuitry and a request ([0025] the write back policy (118) may have a throttling sub-policy (120) that limits the write backs to a time when convenient. For example, if the processor (102) is executing on demand requests, the writing back may be put on hold to free up the cache and non-volatile memory for the on demand requests. An on demand request may be a request that is made by a user (i.e., a host) to be performed by the processor at the time that the user makes the request. In some examples, writing back is performed in the background of the memory device so as to create as little interference with the other operations of the memory device (100). In some examples, the throttling sub-policy (120) allows some interference to be created if the need to write back is great enough and the other operations of the memory device (100) are less urgent)…
Chang et al. do not appear to explicitly teach “to remove data,” “wherein the persistent memory controller is configured to operate using a cache coherent protocol,” and “of a host computing device, the persistent memory controller being separate from the host computing device.” However, Boenapalli et al. disclose:
of a host computing device ([0051] on-demand request from the host device 102), the persistent memory controller being separate from the host computing device (FIG. 1 Device controller 162 of the Flash memory device (corresponding to the persistent memory controller) is separate from the Host device 102).
Chang et al. and Boenapalli et al. are analogous art because Chang et al. teach storing data in persistent hybrid memory and Boenapalli et al. teach a host computing device coupled to a memory device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chang et al. and Boenapalli et al. before him/her, to modify the teachings of Chang et al. with the Boenapalli et al. teachings of a host computing device because implementing a host computing device to send a request to be performed by the processor (i.e., persistent memory controller) would have amounted to little more than combining “familiar elements according to known methods” and would have been obvious because it would have done “no more than yield predictable results.” (MPEP 2143 I.A.) Host computing devices are known to make requests to memory devices. Implementing the host computing device of Boenapalli et al. to send the request of Chang et al. would have yielded the predictable result of providing the request to the processor (i.e., persistent memory controller).
Chang et al. and Boenapalli et al. do not appear to explicitly teach “to remove data” and “wherein the persistent memory controller is configured to operate using a cache coherent protocol.” However, Chen et al. disclose:
to remove data ([0003] data in these locations is written back to the non-volatile memory and then the data is removed from the cache)
Chang et al., Boenapalli et al., and Chen et al. are analogous art because Chang et al. teach storing data in persistent hybrid memory; Boenapalli et al. teach a host computing device coupled to a memory device; and Chen et al. teach cache flushing is a solid state memory device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chang et al., Boenapalli et al., and Chen et al. before him/her, to modify the combined teachings of Chang et al. and Boenapalli et al. with the Chen et al. teachings of removing data when data is written back to nonvolatile memory because doing so would free up space in the cache for subsequent cache writes.
Chang et al., Boenapalli et al., and Chen et al. do not appear to explicitly teach “wherein the persistent memory controller is configured to operate using a cache coherent protocol.” However, Hinkle discloses:
…wherein the persistent memory controller is configured to operate using a cache coherent protocol (FIG. 1 FAR Memory Controller 32; [0036] far memory controller coherent protocol interface that connects the far memory to the host processor may implement the Compute Express Link (CXL) 32 includes at least one processor configured to process the program instructions (see firmware 40), wherein the program instructions are configured to, when processed by the at least one processor, cause the processor to perform various operations. The one or more memory devices 34 may be either volatile or persistent memory devices)…
Chang et al., Boenapalli et al., Chen et al., and Hinkle are analogous art because Chang et al. teach storing data in persistent hybrid memory; Boenapalli et al. teach a host computing device coupled to a memory device; Chen et al. teach cache flushing is a solid state memory device; and Hinkle teaches a cache coherent protocol.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the combined teachings of Chang et al., Boenapalli et al., Chen et al., and Hinkle before him/her, to modify the teachings of Chang et al. and Chen et al. with Hinkle's teachings of implementing cache coherent logic in the persistent memory controller because doing so would increase system performance (Hinkle [0033]).
Regarding claim 2, Chang et al. further disclose:
The persistent memory controller of claim 1, wherein the data controller circuitry processing the request includes the data controller circuitry moving the data based on device idle time (FIG. 10 step 1016 Is processor executing on demand requests?; [0025] the write back policy (118) may have a throttling sub-policy (120) that limits the write backs to a time when convenient. For example, if the processor (102) is executing on demand requests, the writing back may be put on hold to free up the cache and non-volatile memory for the on demand requests. An on demand request may be a request that is made by a user to be performed by the processor at the time that the user makes the request. In some examples, writing back is performed in the background of the memory device so as to create as little interference with the other operations of the memory device (100). In some examples, the throttling sub-policy (120) allows some interference to be created if the need to write back is great enough and the other operations of the memory device (100) are less urgent).
Regarding claim 4, Chang et al. further disclose:
The persistent memory controller of claim 1, wherein the request criterion is based on a pattern of the data in the volatile memory ([0033]; [0050] The policies (606) may also include a write back policy (614) that determines which of the memory blocks in the cache should be written back to the non-volatile memory. In some examples, the write back policy (614) includes determining which of the memory blocks is likely to be finished being modified in the cache. Such a prediction may be based on patterns identified through tracking statistics).
Regarding claim 5, Chang et al. further disclose:
The persistent memory controller of claim 1, wherein the request criterion is based on at least one of:
an age of the data in the volatile memory ([0056] The processor (600) may have a cache usage tracker (630) that tracks the usage of the memory blocks in the cache. Such a tracker (630) may track…the time duration from which the memory block was written back to the non-volatile memory),
a hotness of the data in the volatile memory, or
a selection process selecting the request from the memory manager circuitry.
Regarding claim 6, Chang et al. further disclose:
The persistent memory controller of claim 1, wherein the request criterion is based on a number of requests at the memory manager circuitry ([0056] The processor (600) may have a cache usage tracker (630) that tracks the usage of the memory blocks in the cache. Such a tracker (630) may track the number of writes to a memory block, the number of reads to a memory block)…
Chang et al. do not appear to explicitly teach “a number of requests at a host.” However, Chen et al. further disclose:
a number of requests at the host computing device ([0030] auto-flush function essentially sets the write-back policy so that dirty data is written back after a threshold time period expires and during which no host requests are received).
Regarding claim 7, Chang et al. further disclose:
The persistent memory controller of claim 6, wherein the request criterion is based on a frequency of requests at the memory manager circuitry ([0056] The processor (600) may have a cache usage tracker (630) that tracks the usage of the memory blocks in the cache. Such a tracker (630) may track…the frequency of writes to a memory block, the frequency of reads to a memory block, the clean/dirty status of a memory block)…
Chang et al. do not appear to explicitly teach “a frequency of requests at the host computing device.” However, Chen et al. further disclose:
a frequency of requests at the host computing device ([0030] auto-flush function essentially sets the write-back policy so that dirty data is written back after a threshold time period expires and during which no host requests are received).
Regarding claim 8, Chen et al. further disclose:
The persistent memory controller of claim 6, wherein the request criterion is based on the memory manager circuitry determining a status of the host computing device ([0030] auto-flush function essentially sets the write-back policy so that dirty data is written back after a threshold time period expires and during which no host requests are received).
Regarding claim 9, Chang et al. further disclose:
The persistent memory controller of claim 1, wherein the metadata includes at least one of:
a dirty status of the data in the volatile memory (Fig. 4 metadata 410; [0040] in the cache memory, the metadata fields that indicate that the memory block is dirty may be used when determining which memory blocks to write back to the non-volatile memory),
an age of the data in the volatile memory, or
register metadata that includes at least one of a dirty data count, a hot data count, a host request count, an eviction threshold, or a data hotness threshold.
Regarding claim 10, Chang et al. further disclose:
The persistent memory controller of claim 1, wherein the metadata describes the data in the volatile memory (Fig. 4 metadata 410; [0038] The metadata (410) may track usage statistics about each block (404, 406, 408) in the row (402). For example, the metadata (410) may show the times and the frequency that each block is referenced. The metadata (410) may be updated each time the data is read or written to the memory blocks; [0040] in the cache memory, the metadata fields that indicate that the memory block is dirty may be used when determining which memory blocks to write back to the non-volatile memory).
Regarding claim 11, Chang et al. disclose:
A method for memory management via at least one processor of one or more processors (Fig. 6 Processor 600), the method comprising:
generating metadata (Fig. 6 Cache Usage Tracker 630 of Processor 600; [0056] The processor (600) may have a cache usage tracker (630) that tracks the usage of the memory blocks in the cache) based on monitoring data in volatile memory (Fig. 1 Cache 104; [0018] cache (104), for example, may be a memory cache, a processor memory cache, an off-chip memory cache, a random access memory cache, or combinations thereof. The memory cache may contain data, executable code, other information, or combinations thereof. In some examples, the cache uses dynamic random access memory (DRAM), static random access memory (SRAM), another volatile memory) (Fig. 4 metadata 410; [0038] metadata (410) may track usage statistics about each block (404, 406, 408) in the row (402). For example, the metadata (410) may show the times and the frequency that each block is referenced; [0039] The metadata (410) may include information about whether the memory block has information written to it. For example, a "1" stored in a particular metadata field may indicate that information has been written to the memory block. In some examples, when a memory block has been written to or has been changed, the memory block is referred to as a dirty block. The memory device may use these metadata fields to determine which blocks are dirty);
generating a request to remove the data in the volatile memory based on the metadata ([0040] the metadata fields that indicate that the memory block is dirty may be used when determining which memory blocks to write back to the non-volatile memory); and
processing the request based on the request (Fig. 10 step 1014 Request that dirty blocks are written back to the NVM during a background operation) being allowed to proceed data controller circuitry of a persistent memory controller (Fig. 6 Processor 600) in response to arbitrator circuitry of the persistent memory controller granting of the request based on a request criterion (Fig. 10 step 1016 Is processor executing on demand requests?; Fig. 10 step 1018 Write back selected dirty blocks to NVM)…and wherein the request criterion is based on the request generated by memory manager circuitry the persistent memory controller and a request ([0025] the write back policy (118) may have a throttling sub-policy (120) that limits the write backs to a time when convenient. For example, if the processor (102) is executing on demand requests, the writing back may be put on hold to free up the cache and non-volatile memory for the on demand requests. An on demand request may be a request that is made by a user (i.e., a host) to be performed by the processor at the time that the user makes the request. In some examples, writing back is performed in the background of the memory device so as to create as little interference with the other operations of the memory device (100). In some examples, the throttling sub-policy (120) allows some interference to be created if the need to write back is great enough and the other operations of the memory device (100) are less urgent)…
Chang et al. do not appear to explicitly teach “to remove data,” “wherein the persistent memory controller is configured to operate using a cache coherent protocol,” and “of a host computing device, the persistent memory controller being separate from the host computing device.” However, Boenapalli et al. disclose:
of a host computing device ([0051] on-demand request from the host device 102), the persistent memory controller being separate from the host computing device (FIG. 1 Device controller 162 of the Flash memory device (corresponding to the persistent memory controller) is separate from the Host device 102).
The motivation for combining is based on the same rational presented for rejection of independent claim 1.
Chang et al. and Boenapalli et al. do not appear to explicitly teach “to remove data” and “wherein the persistent memory controller is configured to operate using a cache coherent protocol.” However, Chen et al. disclose:
to remove data ([0003] data in these locations is written back to the non-volatile memory and then the data is removed from the cache)
The motivation for combining is based on the same rational presented for rejection of independent claim 1.
Chang et al., Boenapalli et al., and Chen et al. do not appear to explicitly teach “wherein the persistent memory controller is configured to operate using a cache coherent protocol.” However, Hinkle discloses:
…wherein the persistent memory controller is configured to operate using a cache coherent protocol (FIG. 1 FAR Memory Controller 32; [0036] far memory controller coherent protocol interface that connects the far memory to the host processor may implement the Compute Express Link (CXL) 32 includes at least one processor configured to process the program instructions (see firmware 40), wherein the program instructions are configured to, when processed by the at least one processor, cause the processor to perform various operations. The one or more memory devices 34 may be either volatile or persistent memory devices)…
The motivation for combining is based on the same rational presented for rejection of independent claim 1.
Regarding claim 12, Chang et al. further disclose:
The method of claim 11, wherein processing the request includes moving the data based on device idle time (FIG. 10 step 1016 Is processor executing on demand requests?; [0025] the write back policy (118) may have a throttling sub-policy (120) that limits the write backs to a time when convenient. For example, if the processor (102) is executing on demand requests, the writing back may be put on hold to free up the cache and non-volatile memory for the on demand requests. An on demand request may be a request that is made by a user to be performed by the processor at the time that the user makes the request. In some examples, writing back is performed in the background of the memory device so as to create as little interference with the other operations of the memory device (100). In some examples, the throttling sub-policy (120) allows some interference to be created if the need to write back is great enough and the other operations of the memory device (100) are less urgent).
Regarding claim 13, Chang et al. further disclose:
The method of claim 11, wherein the request criterion is based on at least one of:
a priority of the request generated by the memory manager circuitry and a priority of the request from the host computing device, or a pattern of the data in the volatile memory ([0033]; [0050] The policies (606) may also include a write back policy (614) that determines which of the memory blocks in the cache should be written back to the non-volatile memory. In some examples, the write back policy (614) includes determining which of the memory blocks is likely to be finished being modified in the cache. Such a prediction may be based on patterns identified through tracking statistics).
Regarding claim 14, Chang et al. further disclose:
The method of claim 11, wherein the request criterion is based on at least one of:
an age of the data in the volatile memory ([0056] The processor (600) may have a cache usage tracker (630) that tracks the usage of the memory blocks in the cache. Such a tracker (630) may track…the time duration from which the memory block was written back to the non-volatile memory), or
a hotness of the data in the volatile memory.
Regarding claim 15, Chang et al. further disclose:
The method of claim 11, wherein the request criterion is based on a number of requests at a memory manager circuitry ([0056] The processor (600) may have a cache usage tracker (630) that tracks the usage of the memory blocks in the cache. Such a tracker (630) may track the number of writes to a memory block, the number of reads to a memory block)…
Chang et al. do not appear to explicitly teach “a number of requests at the host computing device.” However, Chen et al. further disclose:
a number of requests at the host computing device ([0030] auto-flush function essentially sets the write-back policy so that dirty data is written back after a threshold time period expires and during which no host requests are received).
Regarding claim 16, Chang et al. further disclose:
The method of claim 15, wherein the request criterion is based on at least one of:
a frequency of requests at the memory manager circuitry ([0056] The processor (600) may have a cache usage tracker (630) that tracks the usage of the memory blocks in the cache. Such a tracker (630) may track the number of writes to a memory block, the number of reads to a memory block) and…or determining the host is in an idle state.
Chang et al. do not appear to explicitly teach “a frequency of requests at the host computing device.” However, Chen et al. further disclose:
a frequency of requests at the host computing device ([0030] auto-flush function essentially sets the write-back policy so that dirty data is written back after a threshold time period expires and during which no host requests are received).
Regarding claim 17, Chang et al. further disclose:
The method of claim 11, wherein the metadata includes at least one of:
a dirty status of the data in the volatile memory (Fig. 4 metadata 410; [0040] in the cache memory, the metadata fields that indicate that the memory block is dirty may be used when determining which memory blocks to write back to the non-volatile memory),or
register metadata that includes at least one of a dirty data count, a hot data count, a host request count, an eviction threshold, or a data hotness threshold.
Regarding claim 18, Chang et al. disclose:
A non-transitory computer-readable medium storing code, the code comprising instructions executable by at least one processor of a device to ([0046] processor (600) may be caused to operate by computer readable program code stored in a computer readable storage medium in communication with the processor (600). The computer readable storage medium may be tangible and/or non-transitory):
generate metadata (Fig. 6 Cache Usage Tracker 630 of Processor 600; [0056] The processor (600) may have a cache usage tracker (630) that tracks the usage of the memory blocks in the cache) based on data monitored in volatile memory (Fig. 1 Cache 104; [0018] cache (104), for example, may be a memory cache, a processor memory cache, an off-chip memory cache, a random access memory cache, or combinations thereof. The memory cache may contain data, executable code, other information, or combinations thereof. In some examples, the cache uses dynamic random access memory (DRAM), static random access memory (SRAM), another volatile memory) (Fig. 4 metadata 410; [0038] metadata (410) may track usage statistics about each block (404, 406, 408) in the row (402). For example, the metadata (410) may show the times and the frequency that each block is referenced; [0039] The metadata (410) may include information about whether the memory block has information written to it. For example, a "1" stored in a particular metadata field may indicate that information has been written to the memory block. In some examples, when a memory block has been written to or has been changed, the memory block is referred to as a dirty block. The memory device may use these metadata fields to determine which blocks are dirty);
generate a request to remove the data in the volatile memory based on the metadata ([0040] the metadata fields that indicate that the memory block is dirty may be used when determining which memory blocks to write back to the non-volatile memory); and
process the request (Fig. 6 Processor 600; Fig. 10 step 1014 Request that dirty blocks are written back to the NVM during a background operation) based on the request being allowed to proceed to data controller circuitry of a persistent memory controller (Fig. 6 Processor 600) in response to arbitrator circuitry of the persistent memory controller granting of the request based on a request criterion (Fig. 10 step 1016 Is processor executing on demand requests?; Fig. 10 step 1018 Write back selected dirty blocks to NVM)…and wherein the request criterion is based on the request generated by memory manager circuitry of the persistent memory controller and a request ([0025] the write back policy (118) may have a throttling sub-policy (120) that limits the write backs to a time when convenient. For example, if the processor (102) is executing on demand requests, the writing back may be put on hold to free up the cache and non-volatile memory for the on demand requests. An on demand request may be a request that is made by a user (i.e., a host) to be performed by the processor at the time that the user makes the request. In some examples, writing back is performed in the background of the memory device so as to create as little interference with the other operations of the memory device (100). In some examples, the throttling sub-policy (120) allows some interference to be created if the need to write back is great enough and the other operations of the memory device (100) are less urgent)…
Chang et al. do not appear to explicitly teach “to remove data,” “wherein the persistent memory controller is configured to operate using a cache coherent protocol,” and “of a host computing device, the persistent memory controller being separate from the host computing device.” However, Boenapalli et al. disclose:
of a host computing device ([0051] on-demand request from the host device 102), the persistent memory controller being separate from the host computing device (FIG. 1 Device controller 162 of the Flash memory device (corresponding to the persistent memory controller) is separate from the Host device 102).
The motivation for combining is based on the same rational presented for rejection of independent claim 1.
Chang et al. and Boenapalli et al. do not appear to explicitly teach “to remove data” and “wherein the persistent memory controller is configured to operate using a cache coherent protocol.” However, Chen et al. disclose:
to remove data ([0003] data in these locations is written back to the non-volatile memory and then the data is removed from the cache)
The motivation for combining is based on the same rational presented for rejection of independent claim 1.
Chang et al., Boenapalli et al., and Chen et al. do not appear to explicitly teach “wherein the persistent memory controller is configured to operate using a cache coherent protocol.” However, Hinkle discloses:
…wherein the persistent memory controller is configured to operate using a cache coherent protocol (FIG. 1 FAR Memory Controller 32; [0036] far memory controller coherent protocol interface that connects the far memory to the host processor may implement the Compute Express Link (CXL) 32 includes at least one processor configured to process the program instructions (see firmware 40), wherein the program instructions are configured to, when processed by the at least one processor, cause the processor to perform various operations. The one or more memory devices 34 may be either volatile or persistent memory devices)…
The motivation for combining is based on the same rational presented for rejection of independent claim 1.
Regarding claim 19, Chang et al. further disclose:
The non-transitory computer-readable medium of claim 18, wherein processing the request generated by the memory manager circuitry is based on further instructions executable by the at least one processor of the device to move the data during an idle time of the device (FIG. 10 step 1016 Is processor executing on demand requests?; [0025] the write back policy (118) may have a throttling sub-policy (120) that limits the write backs to a time when convenient. For example, if the processor (102) is executing on demand requests, the writing back may be put on hold to free up the cache and non-volatile memory for the on demand requests. An on demand request may be a request that is made by a user to be performed by the processor at the time that the user makes the request. In some examples, writing back is performed in the background of the memory device so as to create as little interference with the other operations of the memory device (100). In some examples, the throttling sub-policy (120) allows some interference to be created if the need to write back is great enough and the other operations of the memory device (100) are less urgent).
Regarding claim 20, Chang et al. further disclose:
The non-transitory computer-readable medium of claim 18, wherein the request criterion is based on at least one of:
a priority of the request generated by the memory manager circuitry and a priority of the request of the host computing device,
a pattern of the data in the volatile memory ([0033]; [0050] The policies (606) may also include a write back policy (614) that determines which of the memory blocks in the cache should be written back to the non-volatile memory. In some examples, the write back policy (614) includes determining which of the memory blocks is likely to be finished being modified in the cache. Such a prediction may be based on patterns identified through tracking statistics),
an age of the data in the volatile memory, or
a hotness of the data in the volatile memory.
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the examiner’s statement of reasons for allowance:
While one or more reasons are offered below citing reasons that the claims are allowable over the prior art, it is each claim taken as a whole, including interrelationships and interconnections between various claimed elements, which are allowable over the prior art of record and not any individual limitation of a claim. The prior art of Chang et al., Boenapalli et al., Chen et al., and Hinkle, when taken alone or in combination with each other, fail to anticipate and/or make obvious to one of ordinary skill in the art the claimed invention prior to the effective filing date.
Regarding claim 3, the prior art, alone or in combination, does not disclose the following limitations, as claimed, in combination with the other claimed limitations:
“The persistent memory controller of claim 1, wherein the request criterion is based on a priority of the request generated by the memory manager circuitry and a priority of the request from the host computing device.”
Response to Arguments
Applicant’s arguments, filed April 29, 2026, with respect to the rejection(s) of claim(s) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chang et al., Boenapalli et al., Chen et al., and Hinkle.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TRACY A WARREN/Primary Examiner, Art Unit 2137
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