Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 and 16-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "wherein while the read voltages having different levels are sequentially applied to the selected word line, the levels of the unselected word lines are maintained at the pass voltage". There is insufficient antecedent basis for this limitation in the claim. The claim does not previously set forth a claim limitation wherein the read voltages having different levels are sequentially applied to the selected word line, which renders the meaning of the claim limitation “wherein while the read voltages having different levels are sequentially applied to the selected word line, the levels of the unselected word lines are maintained at the pass voltage” unclear as to not clear and obvious to one of ordinary skill in the art when/how the sequential application occurs. Appropriate clarification is required.
Claims 2-8 are rejected as dependent upon claim 1.
Claim 16 sets forth “a latch for sensing included in the page buffer”. Claim 15, upon which claim 16 depends, sets forth “a cache latch included in a page buffer”. It is unclear if both instances are intended to refer to the cache latch of claim 15. Appropriate clarification is required.
Claim 17 sets forth “the latch”, “a cache latch included in a page buffer”, and “the latch”. This language is unclear. Claim 15, upon which claim 17 depends, sets forth “a cache latch included in a page buffer.” It is unclear if all instances of “a cache latch/latch” are intended to refer to the cache latch of claim 15. Appropriate clarification is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ahn (US 20230386561).
Regarding claim 14, Ahn teaches an operating method of a semiconductor device, (Ahn, FIG. 1-3) the operating method (“operation of the semiconductor memory device”) comprising: receiving a read command; (Ahn, “a read command”) outputting data sensed in a previous read command in response to the read command; (Ahn, [0017]: “a controller outputting a first type of read command and an operation of a semiconductor memory device based on the first type of read command in accordance with an embodiment of the present disclosure.”; [0049]: “ During the read operation, the read and write circuit 130 may sense data of the memory cell, temporarily store the read data, and output data DATA to the input/output buffer (not shown) of the semiconductor memory device 100. In an exemplary embodiment, the read and write circuit 130 may include a column selection circuit, and the like, in addition to the page buffers (or page registers).”) and sensing data by sequentially providing a selected word line with read voltages having different levels in response to the read command. (Ahn, for example [0081]: “Referring to FIG. 6, the read operation may be performed in a method similar to the operation method as shown in FIG. 5, except that read voltages may be sequentially applied to the selected word line from the highest read voltage R3 to the lowest read voltage R1. Therefore, overlapping descriptions have been omitted.”)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220130463 A1 (Kim, et al., hereinafter Kim) in view of US 20220180929 (Xiang, et al., hereinafter Xiang).
Regarding claim 9, Kim teaches an operating method of a semiconductor device, (Kim, “non-volatile memory device”) the operating method comprising: receiving a read command (Kim, “A non-volatile memory device receives a read command”) that instructs to consecutively output multi-bit data stored in a memory cell of a memory string (Kim, “NAND memory string”) coupled to a plurality of word lines; (Kim, FIG. 3; Kim, [0058]: “Each of the plurality of NAND memory strings NS11 to NS33 may include the string select transistor SST, the plurality of memory cells MC1 to MC8,”) providing a pass voltage to unselected word lines of the plurality of word lines until an operation corresponding to the read command is completed; (Kim, [0006]: “The read method may further include applying the read pass voltage to the at least one word line, applying a first read level to the selected word line,…”) and sequentially providing a selected word line of the plurality of word lines with read voltages having different levels to sequentially determine the multi-bit data, (Kim, [0006]: “According to an exemplary embodiment of the present disclosure, a read method of a non-volatile memory device may include applying, in a state in which a read pass voltage is applied to a word line selected according to an address, a first aggressor group read level to at least one word line adjacent to the selected word line, and obtaining first aggressor group information from a memory cell connected to the at least one word line…The read method may further include applying, in a state in which the read pass voltage is applied to the selected word line, a second aggressor group read level to the at least one word line, and obtaining second aggressor group information from the memory cell connected to the at least one word line…The read method may further include applying the read pass voltage to the at least one word line, applying a third read level to the selected word line, and performing a third read operation…”). Kim does not appear to teach while the levels of the unselected word lines are maintained at the pass voltage.
Xiang cures the deficiencies of Kim. Xiang teaches while the levels of the unselected word lines are maintained at the pass voltage. (Xiang, [0071]: “After a period of charging time, the voltage on the unselected word lines rises to the pass voltage and maintains at the pass voltage.”)
Both Kim and Xiang are directed to non-volatile memory devices and operating methods. One of ordinary skill in the art would find it obvious to combine the operating method of a semiconductor device of Kim with the maintaining of unselected word lines at a pass voltage of Xiang with the motivation of improving functionality of the semiconductor memory device.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Xiang in view of US 20130094294 A1 (Kwak, et al., hereinafter Kwak).
Regarding claim 10, Kim/Xiang teaches the operating method of claim 9, but does not appear to explicitly teach wherein the multi-bit data comprise a least significant bit (LSB), a central significant bit (CSB), and a most significant bit (MSB).
Kwak cures the deficiencies of Kim/Xiang. Kwak teaches wherein the multi-bit data comprise a least significant bit (LSB), a central significant bit (CSB), and a most significant bit (MSB). (Kwak, [0145]: “For example, the upper verification voltage VFYU may indicate a set of voltages with various levels respectively corresponding to a Least Significant Bit (LSB), a Central Significant Bit (CSB), and a Most Significant Bit (MSB). These bits may also be referred to by different names, such as Second Significant Bit (2SB). In general, use of these "significant bit" phrases are used in this application to distinguish programming of various bits of information into the multi-level cell.”)
It would have been obvious at the effective filing date to combine the non-volatile memory device of Kim/Xiang with the teachings of Kwak, specifically the naming of the significant bit phrases, to “distinguish programming of various bits of information into the multi-level cell” as set forth by Kwak. The non-volatile memory device of Kim/Xiang, while including “multi-bit” memory cells, does not specifically define “significant bit” phrases to distinguish bits of information in the multi-bit cell. However, it would be obvious to one of ordinary skill in the art to combine the naming conventions of Kwak with the multi-bit cells as set forth in Kim/Xiang for the purposes of clarifying the invention.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Xiang in view of Kwak further in view of US 20210241834 A1 (Sang Sik Kim, et al., hereinafter Sang).
Regarding claim 11, Kim/Xiang/Kwak teaches the operating method of claim 10, but does not appear to teach wherein the read voltages include first to seventh read voltages having different levels; and each of the seventh read voltage and the third read voltage is used for determining the LSB, each of the sixth read voltage, the fourth read voltage, and the second read voltage is used for determining the CSB, and each of the fifth read voltage and the first read voltage is used for determining the MSB.
Sang cures the deficiencies of Kim/Xiang/Kwak. Sang teaches wherein the read voltages include first to seventh read voltages having different levels; (Sang, [0079]: “seven read voltages) each of the seventh read voltage and the third read voltage is used for determining the LSB; each of the sixth read voltage, the fourth read voltage, and the second read voltage is used for determining the CSB; and each of the fifth read voltage and the first read voltage is used for determining the MSB. (Sang, [0079]: “Further, as described above with reference to FIG. 6, in the TLC memory device, seven read voltages are required to identify a value of LSB data, a value of CSB data and a value of MSB data stored in each memory cell. The third and seventh read voltages R3 and R7 may be used to identify a value of LSB data in a read operation on the first logic page, and the second, fourth and sixth read voltages R2, R4 and R6 may be used to identify a value of CSB data in a read operation on the second logic page. The first and fifth read voltages R1 and R5 may be used to identify a value of MSB data in a read operation on the third logic page.”)
It would have been obvious to one of ordinary skill in the art at the effective filing date to combine the teachings of Kim/Xiang/Kwak with the application of seven read voltages as taught in Sang. Sang, like Kim/Xiang/Kwak, is directed to a memory system and operating method thereof. One of ordinary skill in the art would find it obvious to combine the seven read voltages of Sang with the motivation of identifying the values of the LSB, CSB, and MSB data in an efficient method.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ahn in view of KR 20120005823 A (Jung).
Regarding claim 15, Ahn teaches the operating method of claim 14, but does not appear to teach wherein outputting data comprises outputting data stored in a cache latch included in a page buffer.
Jung cures the deficiencies of Ahn. Jung teaches wherein outputting data comprises outputting data stored in a cache latch included in a page buffer. (Jung, “According to an embodiment of the present invention, a method of operating a flash memory device may include storing data of memory cells connected to a selected word line of a memory block in a main latch unit. Storing repair information in the temporary latch unit, and outputting data stored in the main latch unit through the cache latch unit while an erase operation of the memory block is performed.”)
Both Ahn and Jung are directed to memory devices and methods of operating such memory devices. It would have been obvious to one of ordinary skill in the art to combine the operating method of Ahn with the outputting of data stored in a cache latch of Jung with the motivation of improving functionality of the memory device.
Allowable Subject Matter
Claims 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J KING whose telephone number is (703)756-1232. The examiner can normally be reached M-F 9am-5pm.
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/DANIEL JOHN KING/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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