DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dykstra (US 18305139).
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With respect to claim 1, fig. 2 of Dykstra (US 18305139) discloses a high frequency module comprising: a first capacitor (235) including a first end connected to a first signal line (through to 205); a second capacitor (240) including a first end connected to a second signal line (through to 210); a first switch (217) provided between a second end of the first capacitor and a reference potential (VDD or GND); a second switch (218) provided between a second end of the second capacitor and the reference potential (VDD or GND); an inspection terminal (between 218 and 219) configured to allow inspection of both the first switch and the second switch; and a resistor (between VDD, 217 and 218) connected between the first capacitor (235) and the first switch (217), wherein the resistor includes; a first end connected between the second capacitor and the second switch,; and a second end connected between the first capacitor and the first switch. ( Note: the resistance between 217 and 218 can be considered a single resistor. Alternatively, the single resistor between 217 and VDD, is connected to 240 and 218 via the resistor between VDD and 218 (i.e. no direct connection is stipulated in the claim language)).
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ito (US 10771013).
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With respect to claim 1, fig. 11 of Ito (US 10771013) discloses a high frequency module comprising: a first capacitor (213) including a first end connected to a first signal line (at XG); a second capacitor (214) including a first end connected to a second signal line (at XD); a first switch (251-1) provided between a second end of the first capacitor and a reference potential (GND); a second switch (261-1) provided between a second end of the second capacitor and the reference potential (GND); an inspection terminal (inspection terminals electrically connected to both ends of the resonator 3) configured to allow inspection of both the first switch and the second switch; and a resistor (212) connected between the first capacitor and the first switch, wherein the resistor (212) includes: a first end connected between the second capacitor and the second switch; and a second end connected between the first capacitor and the first switch.
With respect to claim 2, fig. 11 of Ito discloses the high frequency module according to Claim 1, wherein the inspection terminal (3) is electrically connected to a first end of the resistor (212).
With respect to claim 3, fig. 11 of Ito discloses the high frequency module according to Claim 2, further comprising: a current limit resistor (constant current source 218 would function as a current limit resistor in total, i.e. a variable resistor based on the SELB input), wherein the current limit resistor is connected between the inspection terminal and an inspection system, or the current limit resistor is connected between the inspection terminal (3) and the connection point between the second capacitor (214) and the second switch (261-1).
With respect to claim 4, fig. 11 of Ito discloses the high frequency module according to Claim 3, wherein a resistance value of the resistor (212) is higher than a resistance value of the current limit resistor (218). (Here, 218 can be selected to have a lower resistance value and 212 can be selected to have a higher resistance value as this is within the scope of the art to select the resistance values as such. )
With respect to claim 5, figs. 4 and 11 of Ito discloses the high frequency module according to Claim 1, further comprising an amplifier circuit (211), wherein the first signal line is connected to the amplifier circuit (at XG), and the first signal line is a power source voltage supply line (see fig. 4 showing wherein VCC is connected to XG).
With respect to claim 6, Ito discloses the high frequency module according to Claim 5, wherein the first signal line (at XG) is further connected to a power source terminal (VCC) to supply power to the amplifier circuit (211), and the amplifier circuit is configured to control the power source voltage in a first mode (external communication mode) and a second mode (DLD inspection mode ). (see col. 7 lines 58-63)
With respect to claim 7, Ito discloses the high frequency module according to Claim 6, wherein the first mode is an envelope tracking (ET) type power amplification mode (“in a case where a control signal with a predetermined pattern is input from the external terminal OE of the oscillator 1 (OE terminal of the oscillation IC 2) within a predetermined period after the start of supply of the power supply voltage to the external terminal VCC of the oscillator 1 (VCC terminal of the oscillation IC 2) (that is, within a predetermined period after the power is supplied), after the predetermined period elapses, the control circuit 23 sets the operation mode of the oscillator 1 (oscillation IC 2) to the external communication mode. For example, the control circuit 23 may set, a period for which the resonator 3 starts to oscillate by power supply from the oscillator 1 (oscillation IC 2) and it is detected that the oscillation is stabilized (for example, the oscillation signal has a desired amplitude), as the predetermined period.” (col. 7, lines 63- col. 8 line 10)) that controls the power source voltage according on an amplitude level of an input signal (SELB).
With respect to claim 8, Ito discloses the high frequency module according to Claim 7, wherein the second mode (DLD inspection mode or normal mode) is an average power tracking type power amplification mode (“In addition, the control circuit 23 performs sampling of the serial data signal for each edge of the serial clock signal, based on, for example, inter-integrated circuit (I.sup.2C) bus standard, and performs processing such as setting of the operation mode and setting of control data in each operation mode, based on a command and data which are obtained by the sampling. For example, the control circuit 23 sets the operation mode of the oscillator 1 (oscillation IC 2) to the corresponding mode by sampling a command for transition of the operation mode of the oscillator 1 (oscillation IC 2) to the corresponding mode (the normal operation mode, the DLD inspection mode, or the like).” (col. 8, lines )) that controls the power source voltage according to an average output power.(Here, the sampling of the oscillation current is considered average power tracking )
With respect to claim 9, Ito discloses the high frequency module according to Claim 1, wherein the first signal line is a power source voltage supply line (XG is connected to VCC) of an amplifier circuit (212), and the second signal line (XE) is a high frequency signal transmission line.
With respect to claim 10, fig. 11 of Ito discloses a high frequency module comprising: a first capacitor (213) including a first end connected to a first signal line (at XG); a second capacitor (214) including a first end connected to a second signal line (at XD); a first switch (251-1) provided between a second end of the first capacitor and a reference potential (at GND); a second switch (261-1) provided between a second end of the second capacitor and the reference potential (at GND); an inspection terminal (nspection terminals electrically connected to both ends of the resonator 3)) configured to allow inspection of both the first switch (251-1) and the second switch (261-1); a first resistor (212); and a second resistor (218, variable current source is a variable resistor), wherein the first resistor and the second resistor are connected in series between a connection point (at 212) between the first capacitor (213) and the first switch(251-1) and a connection point (at 212) between the second capacitor (214) and the second switch (261-1), and the first resistor includes: a first end connected between the second capacitor and the second switch; and a second end connected between the first capacitor and the first switch. .
With respect to claim 11, Ito discloses the high frequency module according to Claim 10, wherein the inspection terminal (inspection terminals at both ends of 3) is electrically connected to a connection point (at 212) between the first resistor (212) and the second resistor (218).
With respect to claim 12, Ito discloses the high frequency module according to Claim 10, wherein the inspection terminal (inspection terminals electrically connected to both ends of the resonator 3) is connected between an inspection system (21 detailed in fig. 9) and the connection point between the first resistor (212) and the second resistor (218).
With respect to claim 13, Ito discloses the high frequency module according to Claim 10, further comprising: a current limit resistor (part of 218 limiting current according to SELB) connected between the connection point between the first resistor (212) and the second resistor (part of 218 selected), and the inspection terminal (inspection terminals electrically connected to both ends of the resonator 3).
With respect to claim 14, Ito discloses the high frequency module according to Claim 13, wherein resistance values of the first resistor (212) and the second resistor (218) are higher than a resistance value of the current limit resistor (part of 218 limiting current according to SELB). (Here, the resistance of the second resistor can be selected to have a lower resistance value and 212 can be selected to have a higher resistance value as this is within the scope of the art to select the resistance values as such. )
With respect to claim 15, Ito discloses the high frequency module according to Claim 10, further comprising an amplifier circuit (211), wherein the first signal line is connected to the amplifier circuit, and the first signal line is a power source voltage supply line (see fig. 4, wherein VCC is connected to VCC).
With respect to claim 16, Ito discloses the high frequency module according to Claim 15, wherein the first signal line (at XG) is connected to a power source terminal (at VCC) to supply power to the amplifier circuit (211), and the amplifier circuit is configured to control the power source voltage in a first mode (external communication mode) and a second mode (DLD inspection mode ). (see col. 7 lines 58-63)
With respect to claim 17, Ito discloses the high frequency module according to Claim 16, wherein the first mode is an envelope tracking (ET) type power amplification mode (“in a case where a control signal with a predetermined pattern is input from the external terminal OE of the oscillator 1 (OE terminal of the oscillation IC 2) within a predetermined period after the start of supply of the power supply voltage to the external terminal VCC of the oscillator 1 (VCC terminal of the oscillation IC 2) (that is, within a predetermined period after the power is supplied), after the predetermined period elapses, the control circuit 23 sets the operation mode of the oscillator 1 (oscillation IC 2) to the external communication mode. For example, the control circuit 23 may set, a period for which the resonator 3 starts to oscillate by power supply from the oscillator 1 (oscillation IC 2) and it is detected that the oscillation is stabilized (for example, the oscillation signal has a desired amplitude), as the predetermined period.” (col. 7, lines 63- col. 8 line 10)) that controls the power source voltage according on an amplitude level of an input signal (SELB).
With respect to claim 18, Ito discloses the high frequency module according to Claim 17, wherein the second mode (DLD inspection mode or normal mode) is an average power tracking type power amplification mode (“In addition, the control circuit 23 performs sampling of the serial data signal for each edge of the serial clock signal, based on, for example, inter-integrated circuit (I.sup.2C) bus standard, and performs processing such as setting of the operation mode and setting of control data in each operation mode, based on a command and data which are obtained by the sampling. For example, the control circuit 23 sets the operation mode of the oscillator 1 (oscillation IC 2) to the corresponding mode by sampling a command for transition of the operation mode of the oscillator 1 (oscillation IC 2) to the corresponding mode (the normal operation mode, the DLD inspection mode, or the like).” (col. 8, lines )) that controls the power source voltage according to an average output power.(Here, the sampling of the oscillation current is considered average power tracking )
With respect to claim 19, Ito discloses the high frequency module according to Claim 10, wherein the first signal line (at XG) is a power source voltage supply line (see fig. 4 wherein VCC is connected to XG) of an amplifier circuit (211).
With respect to claim 20, Ito discloses the high frequency module according to Claim 19, wherein the second signal line (at XD) is a high frequency signal transmission line.
Response to Arguments
Applicant's arguments filed 1/23/2026 have been fully considered but they are not persuasive. ]
With respect to Dykstra, the resistor between VDD and 217 is connected between the second capacitor and the second switch via the resistor between VDD 240 and 218. Also both resistances can be considered a single resistor and also read on the claim.
With respect to Ito 212 is connected as such.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAREEM E ALMO/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2849
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