DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 10/24/2025 is acknowledged.
Claims 7-12 and 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 6, 13, 14, and 16 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by MATSUMOTO et al (US 2024/0212938).
Regarding claim 1, MATSUMOTO discloses an electronic component (Fig. 1-5) comprising: an element body (Fig. 1, 10) including a stack (Fig. 4, 14) and a side margin (Fig. 4, 16), the stack having a rectangular or substantially rectangular parallelepiped shape (Fig. 1) and including main surfaces (Fig. 1, top and bottom) opposing each other in a thickness direction (Fig. 1, Z), side surfaces (Fig. 1, front and back in Y direction) opposing each other in a width direction (Fig. 1, Y) orthogonal or substantially orthogonal to the thickness direction (Fig. 1), and end surfaces (Fig. 1, left end and right end) opposing each other in a length direction (Fig. 1, X) orthogonal or substantially orthogonal to the thickness direction and the width direction (Fig. 1), the stack including internal electrode layers (Fig. 2, 12) and a dielectric layer (Fig. 2, 11) stacked in the thickness direction, the side margin covering each of side surfaces of the stack in the width direction (Fig. 4); and an external electrode (Fig. 2, 20a) covering one of the end surfaces of the element body in the length direction and electrically connected to at least one of the internal electrode layers (Fig. 2); wherein the stack includes a first portion (Fig. 4, 142) located at an end in the width direction of the stack in a portion sandwiched between the internal electrode layers in the thickness direction (Fig. 4), and a second portion (Fig. 4, 141) located at a center in the width direction of the stack in the portion sandwiched between the internal electrode layers in the thickness direction (Fig. 4); and an average particle size of dielectric grains included in the first portion is larger than an average particle size of dielectric grains included in the second portion (Fig. 4, and [0046]).
Regarding claim 2, MATSUMOTO further discloses that the stack further includes a third portion (Fig. 4, 16) located at an end in the width direction in the portion sandwiched between the dielectric layers in the thickness direction (Fig. 16); and at least a portion of the end in the width direction of the internal electrode layers is covered with the dielectric grains included in the third portion (Fig. 4).
Regarding claim 4, MATSUMOTO further discloses that an entire or substantially an entire end of the internal electrode layers is covered with the dielectric grains included in the third portion (Fig. 4).
Regarding claim 6, MATSUMOTO further discloses that the average particle size of the dielectric grains included in the first portion is about 200 nm or more and about 1000 nm or less ([0053-0054]).
Regarding claim 13, MATSUMOTO further discloses an additional external electrode (Fig. 2, 20b) covering another one of the end surfaces of the element body in the length direction, the external electrode and the additional external electrode not being in contact with one another (Fig. 2).
Regarding claim 14, MATSUMOTO further discloses that the dielectric later includes an intermediate dielectric layer (Fig. 2, 11), an upper dielectric layer (Fig. 2, 13 on top), and a lower dielectric layer (Fig. 2, 13 on bottom).
Regarding claim 16, MATSUMOTO further discloses that the dielectric later includes 100 or more to 600 or fewer total dielectric layers and the internal electrode layers include 100 or more and 600 or fewer total electrode layers ([0065]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over MATSUMOTO et al (US 2024/0212938) in view of INOMATA et al (US 2023/0081197).
Regarding claim 3, MATSUMOTO fails to teach the claim limitations.
INOMATA teaches that an average particle size of the dielectric grains included in the third portion (Fig. 4, D2) is larger than the average particle size of the dielectric grains included in the second portion (Fig. 4, D1).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of INOMATA to the invention of MATSUMOTO, in order to suppress the appearance of cracks in the capacitor (INOMATA [0012]).
Regarding claim 5, MATSUMOTO fails to teach the claim limitations.
INOMATA teaches that an average particle size of the dielectric grains included in the third portion is larger than a thickness of the internal electrode layers (when D2 is greater than 300nm [0016] and internal electrodes are 300 nm [0017]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of INOMATA to the invention of MATSUMOTO, in order to suppress the appearance of cracks in the capacitor (INOMATA [0012]).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over MATSUMOTO et al (US 2024/0212938) in view of AHN et al (US 2012/0327556).
Regarding claim 15, MATSUMOTO fails to teach the claim limitations.
AHN teaches that a thickness of the intermediate dielectric layer is about 0.3 μm or more and about 0.45 μm or less ([0043]); and a thickness of each of the upper dielectric layer and the lower dielectric layer is about 10 μm or more and about 30 μm or less ([0069]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of AHN to the invention of MATSUMOTO, in order to reduce acoustic noise of the capacitor (AHN [0010]).
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over MATSUMOTO et al (US 2024/0212938) in view of JEON et al (US 2014/0233148).
Regarding claim 17, MATSUMOTO fails to teach the claim limitations.
JEON teaches that one end of each of the internal electrode layers, which is not in contact with the external electrode, is separated from the end surface of the element body by a gap in the length direction of about 5 μm or more and about 30 μm or less (10-60 μm [0143]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of JEON to the invention of MATSUMOTO, in order to increase the reliability of the capacitor (JEON [0013]).
Regarding claim 18, MATSUMOTO fails to teach the claim limitations.
JEON teaches that internal electrode layers include a projected area normal to the thickness direction which is about 80% or more and about 95% or less of a projected area of the dielectric layer normal to the thickness direction (up to 90%-98% body is 600 μm long [0139] margin is 10-60 μm long [0143] so internal electrode is 540-590 μm long or 90-98% the dielectric layer).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of JEON to the invention of MATSUMOTO, in order to increase the reliability of the capacitor (JEON [0013]).
Additional Relevant Prior Art:
LEE et al (US 2015/0348712) teaches relevant art in Fig. 1-4.
UCHIDA (US 2020/0312569) teaches relevant art in Fig. 1-5.
HASHIMOTO (US 2020/0312570) teaches relevant art in Fig. 1-4.
TANIGUCHI (US 2021/0012968) teaches relevant art in Fig. 1-4.
LEE et al (US 2022/0130612) teaches relevant art in Fig. 1-7.
NAM et al (US 2022/0208455) teaches relevant art in Fig. 1-9.
Conclusion
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/MICHAEL P MCFADDEN/Primary Examiner, Art Unit 2848