DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/28/2026 has been entered.
Claim Objections
Claims 1, 17, and 19 are objected to because of the following informalities: “of the non-volatile memory” is repeated twice consecutively. Appropriate correction is required.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot in view of the new grounds of rejection below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-6, 9-11, 15, and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Katz et al (US Pat. Pub. 2012/0008414; hereinafter referred to as Katz) in view of Sharon et al (US Pat. Pub. 2020/0105353; hereinafter referred to as Sharon ‘353) in view of Sharon et al (US Pat. Pub. 2014/0204671; hereinafter referred to as Sharon).
As per claim 1:
Katz teaches a system, comprising:
a non-volatile memory (Fig. 24, 241); and
a controller operatively coupled to the non-volatile memory (Fig. 24, 242), wherein the controller is to:
perform a sequential read operation of a plurality of pages of a block of a plurality of blocks of the non-volatile memory using a first read threshold (paragraph 39);
determine a number of errors during the sequential read operation (paragraph 38), and if the number of errors exceeds a threshold:
determine information on a number of errors for at least a portion of a page (paragraph 160, Nerr) of the sequential read operation (paragraph 54)
determine a second read threshold (Fig. 2, T’1-T’7 and Fig. 18, 184: adjusted threshold based on function f as detailed in paragraph 171) based at least in part on a read histogram for the sequential read operation (Fig. 18, 182 and paragraph 169) and the information on the number of the errors for at least the portion of the page (paragraph 161; Fig. 18 Nerrs(i)).
Not explicitly disclosed is determining a bit error rate (BER) during the sequential read operation. However, Sharon ‘353 in an analogous art teaches computing bit error rate (BER) of a memory by counting a number of errors (paragraph 160). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use BER instead of error count for measuring the performance of the initial read operation of Katz. This modification would have been obvious for one of ordinary skill in the art at the time of filing because BER also uses error count and could have equivalently been substituted, as taught by Sharon.
Also not explicitly disclosed is wherein the controller is further configured to apply the second read threshold to another page of the block, the another page and the portion of the page are of the same sequential read operation. However, Sharon in an analogous art teaches updating read threshold voltages (Fig. 3, 306), and applying the updated read threshold voltage to another page of a block in same sequential read operation (paragraph 43).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the second read thresholdof Katz to read another page of a block in same sequential read operation. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have reduced ECC decoding latency and power consumption (paragraph 43).
As per claim 3: Katz teaches the system of claim 1, wherein the information on the number of the errors for at least the portion of the page comprises a Failed Bit Count (FBC) value (paragraph 160) and a direction of the errors (paragraph 170).
As per claim 4: Katz teaches the system of claim 3, wherein the direction of the errors comprises: a right hand side (r.h.s.) error corresponding a voltage located on a right side of the first threshold along a voltage axis (paragraph 170; increasing read threshold); and a left hand side (l.h.s.) error corresponding a voltage located on a left side of the first threshold along the voltage axis (Fig. 11A and paragraph 170; decreasing read threshold), wherein the voltage axis increases in voltage from the left side to the right side (Fig. 2, VT).
As per claim 5: Katz teaches the system of claim 1, wherein the number of errors for at least a portion of the page comprises an actual number of errors (paragraph 160, Nerr) for a given size of the portion of the page (paragraph 53; a page has an inherent size which is the given size).
As per claim 6: Katz teaches the system of claim 1, wherein determining the information on the number of errors for at least the portion of the page comprises: obtaining read data by performing the sequential read operation (paragraph 54) on the plurality of pages (paragraph 53) using the first read threshold (Fig. 1, T1-T7 and Fig. 18, 184); and obtaining fixed data (paragraph 161; successful error correction) and the information on the number of the errors for at least the portion of the page in response to decoding the read data (paragraph 161; Nerrs (i)).
As per claim 9:
Katz teaches the system of claim 1, wherein the second read threshold is determined based at least in part on the read histogram for the sequential read operation (Fig. 18, 182), the information on the number of the errors for at least the portion of the page (Fig. 18, Nerrs), and the first read threshold (Fig. 18, 184: Thr(i-1)).
As per claim 10: Katz teaches the system of claim 1, wherein the second read threshold is determined for a row of the plurality of pages (paragraph 180).
As per claim 11: Katz teaches the system of claim 1, wherein the controller is to update the first read threshold with the second read threshold for the block (paragraph 58; Fig. 18, 184).
As per claim 15: Katz teaches the system of claim 1, wherein
historical second read thresholds for the block are saved (Fig. 18, 183 Threshold history);
the second read threshold is determined based at least in part of the read histogram (Fig. 18, 182), the information on the number of the errors for at least the portion of the page (Fig. 18, Nerrs(i)), and the historical second read thresholds (Fig. 18, 183 Threshold history);
at least one an estimator or classifier is used to determine the second read threshold (Fig. 18, 183 calculating threshold step performed by estimator hardware such as that in Fig. 24, 242); and
a function is applied on the number of the errors as an input for the estimator (paragraph 171).
As per claim 17:
Latz teaches least one non-transitory computer readable medium including one or more instructions stored thereon and executable by a processor to:
perform a sequential read operation of a plurality of pages of a block of a plurality of blocks of the non-volatile memory using a first read threshold (paragraph 39);
determine a number of errors during the sequential read operation (paragraph 38), and if the number of errors exceeds a threshold:
determine information on a number of errors for at least a portion of a page (paragraph 160, Nerr) of the sequential read operation (paragraph 54);
determine a second read threshold (Fig. 2, T’1-T’7 and Fig. 18, 184: adjusted threshold based on function f as detailed in paragraph 171) based at least in part on read histogram for the sequential read operation (Fig. 18, 182 and paragraph 169) and the information on the number of the errors for at least the portion of the page (paragraph 161; Fig. 18 Nerrs(i)).
Not explicitly disclosed is determining a bit error rate (BER) during the sequential read operation. However, Sharon ‘353 in an analogous art teaches computing bit error rate (BER) of a memory by counting a number of errors (paragraph 160). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use BER instead of error count for measuring the performance of the initial read operation of Katz. This modification would have been obvious for one of ordinary skill in the art at the time of filing because BER also uses error count and could have equivalently been substituted, as taught by Sharon.
Not explicitly disclosed is applying the second read threshold to another page of the block, the another page and the portion of the page are of the same sequential read operation. However, Sharon in an analogous art teaches updating read threshold voltages (Fig. 3, 306), and applying the updated read threshold voltage to another page of a block in same sequential read operation (paragraph 43).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the second read thresholdof Katz to read another page of a block in same sequential read operation. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have reduced ECC decoding latency and power consumption (paragraph 43).
As per claim 18:
Katz teaches at least one non-transitory computer readable medium of claim 17, wherein
the information on the number of the errors for at least the portion of the page comprises a Failed Bit Count (FBC) value (paragraph 160) and a direction of the errors (paragraph 170); and
the direction of the errors comprises:
a right hand side (r.h.s.) error corresponding a voltage located on a right side of the first threshold along a voltage axis (paragraph 170; increasing read threshold); and
a left hand side (l.h.s.) error corresponding a voltage located on a left side of the first threshold along the voltage axis (Fig. 11A and paragraph 170; decreasing read threshold), wherein the voltage axis increases in voltage from the left side to the right side (Fig. 2, VT).
As per claim 19:
Katz teaches a method, comprising:
performing a sequential read operation of a plurality of pages of a block of a plurality of blocks of the non-volatile memory using a first read threshold (paragraph 39);
determining a number of errors during the sequential read operation (paragraph 38), and if the number of errors exceeds a threshold:
determining information on a number of errors for at least a portion of a page (paragraph 160, Nerr) of the sequential read operation (paragraph 54);
determining a second read threshold (Fig. 2, T’1-T’7 and Fig. 18, 184: adjusted threshold based on function f as detailed in paragraph 171) based at least in part on read histogram for the sequential read operation (Fig. 18, 182 and paragraph 169) and the information on the number of the errors for at least the portion of the page (paragraph 161; Fig. 18 Nerrs(i)).
Not explicitly disclosed is determining a bit error rate (BER) during the sequential read operation. However, Sharon ‘353 in an analogous art teaches computing bit error rate (BER) of a memory by counting a number of errors (paragraph 160). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use BER instead of error count for measuring the performance of the initial read operation of Katz. This modification would have been obvious for one of ordinary skill in the art at the time of filing because BER also uses error count and could have equivalently been substituted, as taught by Sharon.
Not explicitly disclosed is applying the second read threshold to another page of the block, the another page and the portion of the page are of the same sequential read operation. However, Sharon in an analogous art teaches updating read threshold voltages (Fig. 3, 306), and applying the updated read threshold voltage to another page of a block in same sequential read operation (paragraph 43).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the second read thresholdof Katz to read another page of a block in same sequential read operation. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have reduced ECC decoding latency and power consumption (paragraph 43).
As per claim 20:
Katz teaches the method of claim 19, wherein
the information on the number of the errors for at least the portion of the page comprises a Failed Bit Count (FBC) value (paragraph 160) and a direction of the errors (paragraph 170); and
the direction of the errors comprises:
a right hand side (r.h.s.) error corresponding a voltage located on a right side of the first threshold along a voltage axis (paragraph 170; increasing read threshold); and
a left hand side (l.h.s.) error corresponding a voltage located on a left side of the first threshold along the voltage axis (Fig. 11A and paragraph 170; decreasing read threshold), wherein the voltage axis increases in voltage from the left side to the right side (Fig. 2, VT).
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Katz in view of Sharon ‘353 in view of Sharon in view of Lee et al (US Pat. Pub. 2020/0258577; hereinafter referred to as Lee).
As per claim 2:
Katz and Sharon teach the system of claim 1. Not explicitly disclosed is wherein the plurality of pages are consecutive pages of the block. However, Lee in an analogous art teaches a sequential read comprising consecutive pages (paragraph 201).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to perform the sequential read of Katz on consecutive pages of the block. This modification would have been obvious for one of ordinary skill in the art at the time of filing because a sequential read is performed on consecutive pages, as shown by Lee.
Claim(s) 7 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Katz in view of Sharon ‘353 in view of Sharon in view of Chan et al (US Pat. Pub. 2014/0325294; hereinafter referred to as Chan).
As per claim 7: Katz and Sharon teach the system of claim 1. Not explicitly disclosed is further comprising saving read data from the sequential read operation and the information on the number of errors for at least the portion of the page in a plurality of buffers. However, Chan in an analogous art teaches saving read data (Fig. 1, 132) and an error count in a buffer (Fig. 3, 31).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to save the read data from the sequential read operation and the information on the number of errors of Katz in a plurality of buffers as done by Chan. This modification would have been obvious for one of ordinary skill in the art at the time of filing because buffer data is suggested by Katz (paragraph 56).
As per claim 13: Katz teaches the system of claim 1. Not explicitly disclosed is wherein the controller is to buffer read data from the sequential read operation of a plurality of blocks comprising the block, one block at a time. However, Chan in an analogous art teaches buffering read data (Fig. 1, 132).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to buffer the read data blocks of Katz one at a time. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Katz teaches performing a sequential read, in which data is read sequentially one block at a time (paragraph 54).
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Katz in view of Sharon ‘353in view of Sharon in view of Ryu (US Pat. Pub. 2018/0158493).
As per claim 8: Katz and Sharon teach the system of claim 7. Not explicitly disclosed is wherein the plurality of buffers comprises: a plurality of data buffers for buffering the read data; an error flag buffer; and an error direction buffer. However, Ryu in an analogous art teaches a read buffer for buffering read data (end of paragraph 52; Fig. 2A, 240), and a buffer table (Fig. 1, 144; Fig. 2, 222; paragraph 70) for storing error flag (Fig. 6) and direction data (paragraphs 54 and 84).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to store the read data, error data, and direction data of Katz in buffers as taught by Ryu. This modification would have been obvious for one of ordinary skill in the art at the time of filing because the information was required by Katz, and doing so would have resulted in expected results without changing the principle of operation.
Claim(s) 12 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Katz in view of Sharon ‘353 in view of Sharon in view of Yamaki et al (US Pat. Pub. 2021/0295942; hereinafter referred to as Yamaki).
As per claim 12: Katz and Sharon teach the system of claim 1. Not explicitly disclosed is wherein the second read threshold is determined by an estimator, wherein the estimator is updated using an iterative training method in which an output of the estimator for an iteration of the iterative training method is used as an input to a subsequent iteration of the iterative training method. However, Yamaki in an analogous art teaches determining a read threshold using an estimator (Fig. 7), wherein the estimator is updated using an iterative training method in which an output of the estimator for an iteration of the iterative training method (Fig. 7, output hnPn-1 of 211) is used as an input to a subsequent iteration of the iterative training method (Fig. 7, output hnPn-1 of 211 input to hn via learner 220).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to estimate the read voltage of Katz using the neural network estimator of Yamaki. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have improved the accuracy of estimating a read voltage (paragraph 17).
As per claim 16: Katz teaches the system of claim 1. Not explicitly disclosed is wherein the second read threshold is determined using a read threshold estimator, the read threshold estimator comprises a linear estimator, a Kalman-type filter or a Deep Neural Network (DNN). However, Yamaki in an analogous art teaches using a read threshold estimator comprising a deep neural network (paragraph 136).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to estimate the read voltage of Katz using a neural network. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have improved the accuracy of estimating a read voltage (paragraph 17).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE N NGUYEN whose telephone number is (571)272-7214. The examiner can normally be reached M-F 9-5.
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/STEVE N NGUYEN/Primary Examiner, Art Unit 2111