Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Papers submitted under 35 U.S.C. 119(a)-(d) have been placed of record in the file.
2. Claims 1-6 are presented for examination.
Title
3. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
4. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to
www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
5. Claims 1-5 and 7 are provisionally rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-6 of copending Application No. 18/609,198. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s) as follows: a memory device using a semiconductor element in which, in plan view on a substrate, a page is composed of a plurality of memory cells arranged in a row direction, and a plurality of pages are arranged in a column direction, wherein each memory cell included in each page comprises: a semiconductor base that, on the base, stands vertically or extends horizontally with respect to the substrate; a first impurity layer and a second impurity layer connected to both ends in an extension direction of the semiconductor base; a gate insulating layer surrounding the semiconductor base; and a first gate conductor layer and a second gate conductor layer that cover the gate insulating layer and that are arranged side by side; the first impurity layer is connected to a source line, the second impurity layer is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer is connected to a selection gate line, and the other is connected to a plate line; voltages applied to the source line, the bit line, the selection gate line, and the plate line are controlled to perform a page erasing operation and a page writing operation; within the semiconductor base, a hole group formed by an impact ionization phenomenon is retained; and logic storage data that is at least three-valued is written and read.VR
The claim 6 of examined application are obvious over the claims of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites the voltage of the plate line is gradually increased during the page reading operation, and determination is performed by the sense amplifier circuit provided on the bit line in an order of the logic storage data with a large number of holes in the hole group retained within the semiconductor base while in the reference was silent. However, Shirota discloses in Fig. 4BC for applying a voltage VReaPL to the plate line and Fig. 6A for sensing.
This is a provisional obviousness-type double patenting rejection because the conflicting claims have not in fact been patented.
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. § 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
7. Claims 1-2 and 4-6 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Shirota et al. US Pub. No. 20230186966 in view of Yang et al. US Pub. No. 20230354599.
As per claims 1-2, Figs. 1 and 6A of Shirota are directed to a memory device (abstract) using a semiconductor element (Fig. 1) in which, in plan view on a substrate (1), a page (Fig. 6A) is composed of a plurality of memory cells (C00-C22) arranged in a row direction (Fig. 6A or 6I, par. 79) , and a plurality of pages are arranged in a column direction (abstract), wherein each memory cell (Fig. 1) included in each page comprises: a semiconductor base (7) that, on the base, stands vertically (Fig. 1) or extends horizontally with respect to the substrate; a first impurity region (3a) and a second impurity region (3b) connected to both ends of the semiconductor base; a gate insulating layer (6a or 6b) surrounding the semiconductor base; and a first gate conductor layer (5a) and a second gate conductor layer (5b) that cover the gate insulating layer and that are arranged side by side; the first impurity region is connected to a source line (SL), the second impurity region is connected to a bit line (BL), one of the first gate conductor layer or the second gate conductor layer is connected to a selection gate line (SG1), and the other is connected to a plate line (PL); voltages applied to the source line, the bit line, the selection gate line, and the plate line are controlled to perform a page erasing operation and a page writing operation (par. 94); within the semiconductor base, a hole group formed by an impact ionization phenomenon or a drain-induced leakage current phenomenon is retained (abstract); l
Shirota fails to disclose logic storage data that is at least three-valued is written and read. However, the abstract of Chang discloses logic storage data that is at least three-valued is written and read. It would have been obvious to a person of ordinary skill in the art at the time invention was made to modify Shirota’s memory device which utilizes the logic storage data having three-valued as taught by Chang in order to increase storage density (par. 13).
As per claim 4, Fig. 5B and a paragraph 65 of Shirota disclose wherein the voltage of the bit line is gradually increased (0.8 V) during the page writing operation.
As per claim 5, Fig. 5B and a paragraph 65 of Shirota disclose wherein the voltage of one or both (2 V) of the selection gate line and the plate line (1.5 V) is gradually increased during the page writing operation.
As per claim 6, Figs. 4BC and 9A to 9C of Shirota disclose wherein: the voltage of the plate line is gradually increased (VReadPL) during the page reading operation, and determination is performed by the sense amplifier circuit (Fig. 6D, par. 76) provided on the bit line in an order of the logic storage data with a large number of holes in the hole group retained within the semiconductor base.
8. Claims 3 and 7 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Shirota et al. US Pub. No. 20230186966 in view of Yang et al. US Pub. No. 20230354599 and further in view of Seo et al. US Patent No. 11024365.
Shirota and Yang fail to disclose wherein the logic storage data is four-valued. However, Fig. 13 and a column 22, lines 27-34 of Seo disclose wherein the logic storage data is four-valued (00, 01, 10 and 11). It would have been obvious to a person of ordinary skill in the art at the time invention was made to modify Shirota and Yang’s memory device which utilizes the logic storage data having four-valued as taught by Seo in order to be used to serve as a cache of the large-capacity storage unit (col. 29, lines 62-63.
9. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
10. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hoai V. Ho whose telephone number is (571) 272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Monday through Thursday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
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/HOAI V HO/Primary Examiner, Art Unit 2827