DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Yao et al. (US 8,487,705 B2), hereinafter Yao.
Regarding claim 1, Yao discloses, in figure 2, a power amplification circuit comprising:
a first transistor (216) that has a base or a gate configured to receive a bias current or a bias voltage (Col. 4, Lines 20-21, “base bias current Ibias suppled to the primary power transistor 216”), and that is configured to amplify an input signal and to output a first current (Col. 2, Lines 65-67, “power transistor 116 [i.e., 216] that serves as a power amplifier for the RF signal”);
a second transistor (208) that has an emitter or a source connected to the base or the gate of the first transistor (source of transistor 208 is connected to the base of transistor 216), and that is configured to supply the bias current or the bias voltage to the base or the gate of the first transistor from the emitter or the source of the second transistor (bias current Ibias is provided to the base of transistor 216 via the source of transistor 208);
a comparison-voltage generation circuit configured to generate a comparison voltage (Vcntl2) based on an emitter or a source current or voltage of the second transistor (Col. 4, Lines 16-19, “control voltage Vcntl2 of the operational amplifier 202, whose value is determined by the maximum base bias current Ibias that flows through the sensing resistor 204 and turns off the base current of the transistor 208”); and
a compensation circuit that is connected to the comparison-voltage generation circuit (amplifier 202 is coupled to comparison voltage Vcntl2) and that is configured to receive the comparison voltage and a reference voltage (amplifier 202 receives Vcntl2 and reference voltage Vref1), and to generate a compensation current that decreases the bias current or the bias voltage based on the comparison voltage and the reference voltage (Col. 4, Lines 14-23, “overdrive protection circuit 200 of FIG. 2 operates by setting the reference voltage Vref1 of the operational amplifier 202 to the control voltage Vcntl2 of the operational amplifier 202, whose value is determined by the maximum base bias current Ibias that flows through the sensing resistor 204 and turns off the base current of the transistor 208. As a result, the base bias current Ibias supplied to the primary power transistor 216 will be shut off under extreme cases of input overdrive, when the sensing resistor 204 senses an extremely high bias current Ibias flowing through it”).
Regarding claim 2, Yao discloses the power amplification circuit according to claim 1, and continues to disclose, in figure 2, wherein the compensation circuit is:
connected to a base or a gate of the second transistor (output of amplifier 202 is connected to the base of transistor 208), and
configured to compensate a second current with the compensation current (current supplied to the base of transistor 208 is adjusted via the amplifier 202…in an overdrive condition the current supplied to the base of transistor 208 is adjusted to prevent the bias current, Ibias, from being supplied to the base of the power transistor 216), the second current being supplied to the base or the gate of the second transistor (operational amplifier 202 outputs to the base of transistor 208).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 & 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yao in view of Miho et al. (US 2011/0006846 A1), hereinafter Miho.
Regarding claim 3, Yao discloses the power amplification circuit according to claim 2, and continues to disclose wherein the compensation circuit is configured to generate the compensation current based on a voltage difference between the comparison voltage and the reference voltage (Col. 4, Lines 14-23, “overdrive protection circuit 200 of FIG. 2 operates by setting the reference voltage Vref1 of the operational amplifier 202 to the control voltage Vcntl2 of the operational amplifier 202, whose value is determined by the maximum base bias current Ibias that flows through the sensing resistor 204 and turns off the base current of the transistor 208. As a result, the base bias current Ibias supplied to the primary power transistor 216 will be shut off under extreme cases of input overdrive, when the sensing resistor 204 senses an extremely high bias current Ibias flowing through it”), but fails to disclose a bias source connected to the base or the gate of the second transistor, and configured to supply the second current to the second transistor; and
wherein the base or the gate of the second transistor is configured to receive the second current to which the compensation current has been added.
However, Miho discloses, in figure 19, a bias source connected to the base or the gate of the second transistor (bias source 85 connected to gate of transistor 91), and configured to supply the second current to the second transistor (supplies a second current to the second transistor 91); and
wherein the base or the gate of the second transistor is configured to receive the second current to which the compensation current has been added (Para [0278], “when the control voltage output terminal 84b of the differential amplifier 84 is connected to the input terminal 87a of the bias circuit 87, the bias current supplied to the base terminal of the amplifying element 93 is generated by the current supplied from the power supply 85 to the base terminal of the NPN bipolar transistor 91. In this case, when the…control voltage Vout_p output from the control voltage output terminal 84b of the differential amplifier 84 increases, the current supplied from the power supply 85 to the base terminal of the NPN bipolar transistor 91 increases by the amount of the increase of the control voltage Vout_p, thereby increasing the bias current supplied to the base terminal of the amplifying element 93.”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the biasing structure of Miho in the power amplification circuit of Yao, to achieve the benefit of adjusting the bias current supplied to the power transistor to increase the gain of the amplification circuit (Miho, Para [0279]).
Regarding claim 8, Yao discloses the power amplification circuit according to claim 1, but fails to disclose wherein the comparison-voltage generation circuit comprises:
a fifth transistor having an emitter or a source connected to ground;
a sixth transistor that has a collector or a drain connected to a base or a gate of the second transistor, and that has an emitter or a source connected to a collector or a drain of the fifth transistor; and
a resistance circuit element between the collector or the drain of the sixth transistor and the compensation circuit.
However, Miho discloses, in figure 19, wherein the comparison-voltage generation circuit comprises (87):
a fifth transistor having an emitter or a source connected to ground (transistor 90 with a source connected to ground));
a sixth transistor that has a collector or a drain connected to a base or a gate of the second transistor (transistor 89 with a drain connected to the base of transistor 91), and that has an emitter or a source connected to a collector or a drain of the fifth transistor (transistor 89 with source connected to the drain of transistor 90); and
a resistance circuit element between the collector or the drain of the sixth transistor and the compensation circuit (resistor 88 connected between the drain of transistor 89 and the compensation circuit 81 in a path to the circuit 81 via bias voltage node 85).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the transistors and resistor of Miho in the comparison-voltage generation circuit of Yao, to achieve the benefit of implementing a bias supplying circuit to control operation of the second transistor (Miho, Para [0239]).
Allowable Subject Matter
Claims 4-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Honda (US 2017/0126183 A1) [Figure 1. Discloses a power amplification circuit includes: a first output transistor that has a power supply voltage supplied to its collector or drain, has a common emitter or source, amplifies an input signal supplied to its base or gate and outputs a first amplified signal from its collector or drain; a first transistor that has the power supply voltage supplied to its collector or drain, has a first current supplied to its base or gate and supplies a first bias current to the base or gate of the first output transistor from its emitter or source; and a second transistor that has its collector or drain connected to the base or gate of the first transistor, has a second current supplied to its base or gate and supplies a second bias current to the base or gate of the first output transistor from its emitter or source.]
Samata (US 2021/0203285 A1) [Figure 2. Discloses a power amplifier circuit includes a first transistor having a first terminal to which a voltage corresponding to a variable power supply voltage is to be supplied and a second terminal to which a radio-frequency signal is to be supplied, the first transistor being configured to amplify the radio-frequency signal, a bias circuit configured to supply a bias current or voltage to the second terminal of the first transistor, and an adjustment circuit configured to adjust the bias current or voltage in accordance with the variable power supply voltage supplied from a power supply terminal.]
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/TYLER J PERENY/ Examiner, Art Unit 2836
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