DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 10-14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 5/22/26.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4-9, 15, 16 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iancu (U.S. PG-PUB NO. 2005/0008098) ion view of Murata (U.S. PATENT NO. 12388491) and further in view of Seely (U.S. PG-PUB NO. 2014/0241469).
-Regarding claim 1, Iancu discloses a test device to analyze radio frequency (RF) signals (FIG. 2), comprising: a multi-channel receiver comprising: a plurality of antennas to receive a plurality of RF input signals (antenna 20, 30, 40, FIG. 2); and a plurality of front ends coupled to the plurality of antennas to receive and pre-process the plurality of RF input signals (front end 22, 34, 44 , FIG. 2); a multiplexer to select a signal of interest among the down-converted plurality of RF input signals (multiplexer 52, paragraph 11).
Iancu is silent to teaching that a plurality of mixers to down-convert the pre-processed plurality of RF input signals; a divider to direct the selected signal of interest to a plurality of analog-digital converter (ADC) channel inputs; and a multi-channel ADC subsystem comprising: a plurality of ADC channels to digitize the signal of interest simultaneously; and a field programmable gate array (FPGA) to combine digital output signals of the plurality of ADC channels. However, the claimed limitation is well known in the art as evidenced by Murata.
In the same field of endeavor, Murata teaches a plurality of mixers to down-convert the pre-processed plurality of RF input signals (mixers 316, 326, 336, 346, FIG. 4); a divider to direct the selected signal of interest to a plurality of analog-digital converter (ADC) channel inputs (signal splitter 105, FIG. 4); and a multi-channel ADC subsystem comprising: a plurality of ADC channels to digitize the signal of interest simultaneously (ADC 114, 124, 134, 144, FIG. 4); and a field programmable gate array (FPGA) to combine digital output signals of the plurality of ADC channels (FPGA, col. 15 lines 60-65).
Therefore, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine the teaching of Iancu with the teaching of Murata in order to reduce or eliminate the uncanceled LO noise caused as a side effect of the path delay compensation.
The combination is silent to teaching that through averaging. However, the claimed limitation is well known in the art as evidenced by Seely.
In the same field of endeavor, Seely teaches through averaging (paragraph 59, FIG. 3).
Therefore, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine the teaching of the combination with the teaching of Seely in order to improve signal-to-noise and improves the quality of the link and range.
-Regarding claim 2, the combination further discloses the FPGA is to average the digital output signals of the plurality of multi-channel ADCs in a single layer of averaging or in multiple layers of averaging (Seely, paragraph 59, FIG. 3).
-Regarding claim 4, the combination further discloses the multiplexer is to provide the signal of interest from two or more of the plurality of antennas to the divider (Iancu, multiplexer 52, paragraph 11).
-Regarding claim 5, the combination further discloses one or more operational subsystems to perform analytical operations on the combined digital output signals (Iancu, digital signal processor (DSP) 50, paragraph 9).
-Regarding claim 6, the combination further discloses one or more operational subsystems include at least one of a display subsystem, an analysis subsystem, a fast Fourier transform (FFT) subsystem, or a storage subsystem (Iancu, digital signal processor (DSP) 50, paragraph 9; Seely, DSP 134, memory device 138, paragraph 48).
-Regarding claim 7, the combination further discloses the FPGA comprises one or more digital processing circuitry to receive and process the combined digital output signals (Seely, digital subsystem 126, FPGA 130, paragraph 48).
-Regarding claim 8, the combination further discloses the test device is a spectrum analyzer (Seely, spectrum assessment, paragraph 134).
-Regarding claim 9, the combination further discloses a plurality of switches to select between an output of the divider and individual outputs of the plurality of front ends (Iancu, switch 32, 42, FIG. 2).
-Regarding claim 15, Iancu discloses a method, comprising: receiving two or more RF input signals through a plurality of antennas of a test device (antenna 20, 30, 40, FIG. 2); receiving a selection of one of the RF input signals as a signal of interest (DSP 50 provides a control signal on line 51 to the multiplexer 52, FIG. 2, paragraph 10-11).
Iancu is silent to teaching that providing the signal of interest to two or more analog-digital converter (ADC) channel inputs of a multi-channel ADC subsystem of the test device; digitizing the signal of interest simultaneously at two or more ADC channels of the multi- channel ADC subsystem; and combining digital output signals of the two or more ADC channels. However, the claimed limitation is well known in the art as evidenced by Murata.
In the same field of endeavor, Murata teaches providing the signal of interest to two or more analog-digital converter (ADC) channel inputs of a multi-channel ADC subsystem of the test device (signal splitter 105, FIG. 4); digitizing the signal of interest simultaneously at two or more ADC channels of the multi- channel ADC subsystem (ADC 114, 124, 134, 144, FIG. 4); and combining digital output signals of the two or more ADC channels (FPGA, col. 15 lines 60-65).
Therefore, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine the teaching of Iancu with the teaching of Murata in order to reduce or eliminate the uncanceled LO noise caused as a side effect of the path delay compensation.
The combination is silent to teaching that averaging the digital output signals. However, the claimed limitation is well known in the art as evidenced by Seely.
In the same field of endeavor, Seely teaches averaging the digital output signals (paragraph 59, FIG. 3).
Therefore, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine the teaching of the combination with the teaching of Seely in order to improve signal-to-noise and improves the quality of the link and range.
-Regarding claim 16, the combination further discloses combining the digital output signals comprises: averaging the digital output signals in a single layer of averaging or in multiple layers of averaging (Seely, paragraph 59, FIG. 3).
-Regarding claim 18, the combination further discloses providing the signal of interest from two or more of the plurality of antennas to the two or more ADC channel inputs through a divider (Iancu, multiplexer 52, paragraph 11).
-Regarding claim 19, the combination further discloses combining the digital output signals at one of a field programmable gate array (FPGA) or a central processing unit (CPU) of the test device (Iancu, digital signal processor (DSP) 50, paragraph 9).
-Regarding claim 20, the combination further discloses selecting the two or more ADC inputs from an output of a divider of the test device and individual outputs of a plurality of front ends of the test device through a plurality of switches (Iancu, switch 32, 42, FIG. 2).
Allowable Subject Matter
Claims 3 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PING Y HSIEH whose telephone number is (571)270-3011. The examiner can normally be reached Monday-Friday, 9am-4pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jennifer Mehmood can be reached at (571) 272-2976. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PING Y HSIEH/ Primary Examiner, Art Unit 2664
Prosecution Insights