DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 3, 4, 5, 6, 11 and 12 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by SUGAMOTO HIROKI (JP 2015056781 A and HIROKI hereinafter.)
As to claim 1, A motor driver circuit, comprising:
a logic circuit, configured to generate a control signal that instructs a high-side transistor to turn on or off; and
a high-side driver, configured to drive the high-side transistor according to the control signal, wherein the high-side driver includes:
a charge pump circuit, configured to generate a boosted voltage according to a clock signal and supply the boosted voltage to a gate of the high-side transistor;
a charging control circuit, configured to stop supplying the clock signal to the charge pump circuit after the control signal instructs the high-side transistor to turn on and after a charging period has elapsed; and
a turn-off circuit, configured to reduce a voltage at the gate of the high-side transistor when the control signal instructs the high-side transistor to turn off.
(As to claim 1, HIROKI teaches (figs.1-3, 6, pages 3, 7) A motor driver circuit 100 (high side drive circuit 200, low side drive circuit 300), comprising:
a logic circuit [controller 202] (figs.1,2, 3) configured to generate a control signal [Son/Soff] (based on control signal SCNT, see Figs.1-3) that instructs a high-side transistor [MH] to turn on or off (See, page 2 para’s [10-11]); and
a high-side driver 200 (see fig.3), configured to drive the high-side transistor [MH] according to the control signal SCNT (see fig.2), wherein the high-side driver 200 (fig.3, 6) includes:
a charge pump circuit 206 (210) (figs.1, 3), configured to generate a boosted voltage [VG1] (see fig.2, page 2, para. 10, & page 5, para’s 1-3) according to a clock signal [CLK] (fig.3) and supply the boosted voltage [VG1] (see fig.2, and description of embodiment fig.3, pages 2-4) to a gate of the high-side transistor [MH];
a charging control circuit [controller 202, 220] (see figs.1, 3), configured to stop supplying (cutoff) the clock signal [CLK] to the charge pump circuit 206 (210) after the control signal SCNT instructs the high-side transistor [MH] to turn on and after a charging period [t0-t2] has elapsed (when Sw1 is on at t0 to t2, high side transistor [MH] is on at time t1-t2, see fig.2, page 2, para’s 10-12, page 3, para. 1); and
a turn-off circuit [control section 224] (see fig.3), configured to lower a voltage VG1 at the gate of the high-side transistor [MH] when the control signal SCNT (see fig.2) instructs the high-side transistor [MH] to turn off (fig.2 shows voltage VG1 is lowered at time t2, when SW1 is off wherein high side transistor [MH] is off at time t3, (see fig.2, page 2, para’s 11-12, page 3, para.1)).
As to claim 2, The motor driver circuit of Claim 1, comprising: an oscillator, configured to generate the clock signal; and a first switch, connected between an output node of the oscillator and an input node of a clock of the charge pump circuit, wherein the charging control circuit is configured to control the first switch.
(As to claim 2, HIROKI teaches (figs.1-3, 6, pages 3, 7) A motor driver circuit 100 (200, 300), comprising:
an oscillator 204 (figs.1, 3), configured to generate the clock signal [CLK]; and a first switch SW1/216 (figs.1, 3), connected between an output node of the oscillator 204 and an input node of a clock [CK] of the charge pump circuit 210 (206), wherein the charging control circuit [controller 202/220] is configured to control the first switch [SW1/216] (fig.2)).
As to claim 3, The motor driver circuit of Claim 1, wherein the charging control circuit is configured to end the charging period when a predetermined time has elapsed since the control signal instructed to turn on the high-side transistor.
(As to claim 3, HIROKI teaches (figs.1-3, 6, pages 3, 7) A motor driver circuit 100 (200, 300), wherein the charging control circuit [controller 202/220] (fig.3) is configured to end the charging period (discharging at time t2, see fig.2) when a predetermined time [t0-t2] has elapsed since the control signal SCNT instructed to turn on the high-side transistor [MH] (i.e. when Sw1 is turned on, high side-transistor MH (see figs.1, 2 & 3) is turned on for charging period t0-t2, see fig.2)).
As to claim 4, The motor driver circuit of Claim 2, wherein the charging control circuit is configured to end the charging period when a predetermined time has elapsed since the control signal instructed to turn on the high-side transistor.
(As to claim 4, HIROKI teaches (figs.1-3, 6, pages 3, 7) A motor driver circuit 100 (200, 300), wherein the charging control circuit [controller 202/220] is configured to end the charging period (discharging at time t2, see fig.2) when a predetermined time [t0-t2] has elapsed since the control signal SCNT instructed to turn on the high-side transistor [MH] (i.e. when Sw1 is turned on, high side-transistor MH (see figs.1, 2 & 3) is turned on for charging period t0-t2, see fig.2)).
As to claim 5, The motor driver circuit of Claim 1, wherein the charging control circuit is configured to end the charging period when the voltage at the gate of the high-side transistor reaches a predetermined level.
(As to claim 5, HIROKI teaches (figs.1-3, 6, pages 3, 7) A motor driver circuit 100 (200, 300), wherein the charging control circuit [controller 202/220] (FIGS.1, 3) is configured to end the charging period (discharging at time t2, see fig.2) when the voltage VG1 (see fig.2) at the gate of the high-side transistor [MH] (figs.1, 2 & 3) lowered to reach a predetermined level [VOUT+ VTH]).
As to claim 6, The motor driver circuit of Claim 2, wherein the charging control circuit is configured to end the charging period when the voltage at the gate of the high-side transistor reaches a predetermined level.
(As to claim 6, HIROKI teaches (figs.1-3, 6, pages 3, 7) A motor driver circuit 100 (200, 300), wherein the charging control circuit [controller 202/220] (FIGS.1, 3) is configured to end the charging period (discharging at time t2, see fig.2) when the voltage VG1 (see fig.2) at the gate of the high-side transistor [MH] (figs.1, 2 & 3) lowered to reach a predetermined level [VOUT+ VTH]).
As to claim 11, The motor driver circuit of Claim 1, wherein the motor driver circuit is integrated on one semiconductor substrate.
(As to claim 11, HIROKI teaches (fig.3/6) A motor driver circuit (200/300), wherein
the motor driver circuit 200/300 is integrated on one semiconductor substrate 100/400 (see claim 17, page 13)).
As to claim 12, The motor driver circuit of Claim 2, wherein the motor driver circuit is integrated on one semiconductor substrate.
(As to claim 12, HIROKI teaches (fig.3/6) A motor driver circuit (200/300), wherein
the motor driver circuit 200/300 is integrated on one semiconductor substrate 100/400 (see claim 17, page 13)).
Allowable Subject-Matter
Claims 7, 8, 9, and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: As to claim 7, SUGAMOTO HIROKI (JP 2015056781 A) fails to teach the turn-off circuit includes a second switch connected between the gate of the high-side transistor and a ground, or between the gate and a source of the high-side transistor.
As to claim 8, SUGAMOTO HIROKI (JP 2015056781 A) fails to teach the turn-off circuit includes a second switch connected between the gate of the high-side transistor and a ground, or between the gate and a source of the high-side transistor.
As to claim 9, SUGAMOTO HIROKI (JP 2015056781 A) fails to teach a third switch connected between the reference input node of the charge pump circuit and a drain of the high-side transistor, the charging control circuit is configured to turn on the third switch when the control signal instructs the high-side transistor to turn on and in combination with the other limitations of claim 9.
As to claim 10, SUGAMOTO HIROKI (JP 2015056781 A) fails to teach a third switch connected between the reference input node of the charge pump circuit and a drain of the high-side transistor, the charging control circuit is configured to turn on the third switch when the control signal instructs the high-side transistor to turn on and in combination with the other limitations of claim 10.
Citation of pertinent prior art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. AIURA (US Pub. No. US 2014/0092656 A1:) teaches (figs.1-20, abstract, par’s [0091] thru [0095]) suppress power consumption including a motor driving circuit 2 supplied power from power supply 3 including charge pump 23 (figs.1, 8A-8E).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONY M PAUL whose telephone number is (571)270-1608. The examiner can normally be reached M-F 8 am to 4 pm.
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/ANTONY M PAUL/
Primary Examiner of Art Unit 2846 11/22/2025