Prosecution Insights
Last updated: April 19, 2026
Application No. 18/616,829

SECOND ORDER MODE WAVEGUIDE COUPLING

Non-Final OA §102§103§112
Filed
Mar 26, 2024
Examiner
LEPISTO, RYAN A
Art Unit
2874
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Honeywell International Inc.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
2y 0m
To Grant
96%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
1008 granted / 1146 resolved
+20.0% vs TC avg
Moderate +8% lift
Without
With
+7.7%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
48 currently pending
Career history
1194
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
45.3%
+5.3% vs TC avg
§102
35.6%
-4.4% vs TC avg
§112
11.4%
-28.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1146 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 6, 12 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The term “set just above a cutoff condition” in these claims is a relative term which renders the claim indefinite. The term “just above” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4, 6, 7 and 9-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al (US 2023/0126332 A1). Li teaches: 1, 7, 14. A waveguide coupling system/method of forming the same (100, Figs. 1-2) comprising: integrated photonics chip (104); and forming a waveguide coupler (107, 210) in optical communication with the integrated photonics chip (104), the waveguide coupler (107, 210) including, a base portion (226-1) having a first width, a higher-order portion (226-2) having a second width that is less than the first width of the base portion (226-1) (see Fig. 2), the second width of the higher-order portion (226-2) being set so that higher-order mode energy (TE2) is deconfined to allow for receiving and passing of the higher-order mode energy (TE2, TE1 are received in this portion and TE2 is passed; see Fig. 2; P0029), and a tapered portion between the base portion (226-1) and the higher-order portion (226-2) (see Fig. 2), the tapered portion transitioning between the first width of the base portion (226-1) to the second width of the higher-order portion (226-2); and positioning a light passing medium (226-3, 228-2) to pass (228-2) and receive (226-3) higher-order mode energy (TE2/TE1) with the higher-order portion of the waveguide coupler (226-2). 2/10/17. The waveguide coupler of claim 1/7/16, wherein the higher-order mode energy is second-order mode energy (TE2, TE1). 3/11. The waveguide coupler of claim 1/7, wherein the base portion (226-1) and the higher-order portion (226-2) are generally rectangular in shape (see Fig. 2). 4. The waveguide coupler of claim 1, wherein the waveguide coupler (107, 210) is formed on an integrated photonic chip (104). 6/12/20. The waveguide coupler of claim 1/7/14, wherein the second width of the higher-order portion (226-2) is slightly above a cutoff width that does not support the higher-order mode energy (TE2). Note, what slightly means is undefined. Li teaches this portion drops TE2 mode energy so it is above the cutoff width that does not support this mode (P0029). 9/18/19. The waveguide coupling system of claim 7/14, further comprising: interfacing the higher-order mode energy (TE3, TE2, TE1) to a fundamental-order mode energy (TE0); using an on-chip converter (228, 212) formed in the integrated photonics chip (104), the on-chip converter (228, 212) in optical communication with the waveguide coupler (107/210), the on-chip converter (228, 212) configured to interface between the higher-order mode energy (TE3, TE2, TE1) and a fundamental-order mode energy (TE0) (see Fig. 2). 13/15. The waveguide coupling system of claim 7/14, wherein the second width is further based on a modeling of a width verses higher-order mode (the higher-order modes are passed because of the modelled width, P0029); the second width being set just above a cutoff condition for the higher-order mode based on the modeling of the waveguide width verse higher-order mode so that the higher-order mode energy is deconfined to allow for receiving and passing of the higher-order mode energy. Note, what slightly means is undefined. Li teaches this portion drops TE2 mode energy so it is above the cutoff width that does not support this mode (P0029). 16. The method of claim 14, further comprising: directing a light beam into the waveguide coupler (210); and detecting the higher-order mode energy with the integrated photonics chip (104) (TE3-TE1 is detected by each drop path; P0029). Claims 1-4, 7 and 9-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Onishi (US 9,069,194 B2). Onishi teaches: 1/7. A waveguide coupling system (Figs. 1-2) comprising: integrated photonics chip (10/11); and a waveguide coupler (18, 19, 51) in optical communication with the integrated photonics chip (10/11), the waveguide coupler (18, 19, 51) including, a base portion (18) having a first width, a higher-order portion (51) having a second width that is less than the first width of the base portion (18) (see Fig. 1), the second width of the higher-order portion being set so that higher-order mode energy (TE1) is deconfined to allow for receiving and passing of the higher-order mode energy (TE1) (C6 L54 – C7 L16), and a tapered portion (19) between the base portion (18) and the higher-order portion (51), the tapered portion transitioning between the first width of the base portion (18) to the second width of the higher-order portion (51) (see Fig. 1; C10 L51-58). 2/10. The waveguide coupler of claim 1/7, wherein the higher-order mode energy is second- order mode energy (TE1). 3/11. The waveguide coupler of claim 1/7, wherein the base portion (18) and the higher-order portion (51) are generally rectangular in shape (see Fig. 1). 4. The waveguide coupler of claim 1, wherein the waveguide coupler (18, 19, 51) is formed on an integrated photonic chip (10, 11). 9. The waveguide coupling system of claim 7, further comprising: an on-chip converter (13) formed in the integrated photonics chip (10, 11), the on-chip converter (13) in optical communication with the waveguide coupler (18, 19, 51), the on-chip converter (13) configured to interface between the higher-order mode energy (TE1) and a fundamental-order mode energy (TE0) (C6 L54-65). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 5 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Onishi as applied to claims 1 and 7 above, and further in view of Geng et al (US 2018/0067273 A1). Onishi teaches the waveguide coupler previously discussed. Onishi does not teach expressly an end of the higher-order portion is configured to pass the higher-order mode energy with an optical fiber. Geng teaches a waveguide coupler (100, Fig. 1) wherein a tapered waveguide/high-order portion (120) that deconfines higher-order mode energy (P0045) is configured to be passed to an optical fiber (130) (P0035). Onishi and Geng are analogous art because they are from the same field of endeavor, optical waveguide couplers. At the time of the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the system of Onishi to pass the signal from the higher-order portion to an optical fiber as taught by Geng. The motivation for doing so would have been to allow the preferred mode to be routed off chip. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references teach optical waveguide couplers for deconfining higher-order modes with a tapered waveguide between two non-tapered portions: US 7995625, US 10502895, US 12044887. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN A LEPISTO whose telephone number is (571)272-1946. The examiner can normally be reached on 8AM-5PM EST M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hollweg can be reached on 571-270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RYAN A LEPISTO/Primary Examiner, Art Unit 2874
Read full office action

Prosecution Timeline

Mar 26, 2024
Application Filed
Mar 11, 2026
Non-Final Rejection — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
96%
With Interview (+7.7%)
2y 0m
Median Time to Grant
Low
PTA Risk
Based on 1146 resolved cases by this examiner. Grant probability derived from career allow rate.

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