DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to the rejected claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dai et al (Daoxin Dai, Yongbo Tang, and John E Bowers, "Mode conversion in tapered submicron silicon ridge optical waveguides," Opt. Express 20, 13425-13439 (2012)). Dai teaches:
1/7/14. A waveguide coupler/coupling system/method of forming the same (Fig. 1a) comprising:
integrated photonics chip (Fig. 1a, Section 2A); and
a waveguide coupler (Fig. 1a) in optical communication with the integrated photonics chip (Section 2A), the waveguide coupler including:
a base portion having a first width (W1);
a higher-order portion having a second width (W2) that is less than the first width (W1) of the base portion (see Fig. 1a), the second width of the higher-order portion being selected above a cutoff width for higher-order mode energy for a given degree of confinement provided by the waveguide coupler where the higher-order mode energy is deconfined causing the higher-order mode energy to overlap into a fundamental mode to allow for receiving and passing of the higher-order mode energy (Fig. 7, page 7 paragraph 1); and
a tapered portion (Ltp) between the base portion and the higher-order portion (see Fig. 1a), the tapered portion transitioning between the first width of the base portion to the second width of the higher-order portion (Fig. 1a, Section 2A).
2/10/17. The waveguide coupler of claim 1/7/16, wherein the higher-order mode energy is second-order mode energy (TE2, TE3, TE1) (Fig. 7, page 7 paragraph 1).
3/11. The waveguide coupler of claim 1/7, wherein the base portion and the higher-order portion are generally rectangular in shape (Fig. 1a).
4. The waveguide coupler of claim 1, wherein the waveguide coupler is formed on an integrated photonic chip (Fig. 1a, Section 2A).
5/8. The waveguide coupler of claim 1/7, wherein an end of the higher-order portion is configured to receive and pass the higher-order mode energy with an optical fiber (Section 2A).
6/12/20. The waveguide coupler of claim 1/7/14, wherein the second width of the higher-order portion above the cutoff width does not support the higher-order mode energy (page 5 paragraph 1).
9/19. The waveguide coupling system of claim 7/18, further comprising:
an on-chip converter (the entire structure of Fig. 1a-b, including the buffer, cladding, ridge, etc) formed in the integrated photonics chip, the on-chip converter in optical communication with the waveguide coupler (the taper and waveguide widths only), the on-chip converter configured to interface between the higher-order mode energy and a fundamental-order mode energy (Fig. 7, page 7 paragraph 1).
13. The waveguide coupling system of claim 7, wherein the second width is further based on a modeling of a width verses higher-order mode (page 5 paragraph 1).
15. The method of claim 14, further comprising:
modeling a waveguide width verses higher-order mode to determine the second width (page 5 paragraph 1), the second width being set above a cutoff condition for the higher-order mode based on the modeling of the waveguide width verse higher-order mode so that the higher-order mode energy is deconfined to allow for receiving and passing of the higher-order mode energy (Fig. 7, page 7 paragraph 1).
16. The method of claim 14, further comprising:
directing a light beam into the waveguide coupler (see field profiles of many drawings); and
detecting the higher-order mode energy with the integrated photonics chip (the same field profiles and graphical results shown are “detecting the higher-order mode energy”).
18. The method of claim 14, further comprising:
interfacing the higher-order mode energy to a fundamental-order mode energy (Fig. 7, page 7 paragraph 1).
19. The method of claim 18, further comprising;
using an on-chip converter (the entire structure of Fig. 1a-b, including the buffer, cladding, ridge, etc) to interface the higher-order mode energy to the fundamental-order mode energy (Fig. 7, page 7 paragraph 1).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Toda (US 2023/0083232 A1) teaches the same taper of Dai and references Dai in the disclosure.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN A LEPISTO whose telephone number is (571)272-1946. The examiner can normally be reached 9AM-6PM EST M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hollweg can be reached at 571-270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RYAN A LEPISTO/Primary Examiner, Art Unit 2874