Prosecution Insights
Last updated: October 02, 2026
Application No. 18/616,906

REDUCING COMPUTATION COMPLEXITY AND INCREASING POWER EFFICIENCY IN MULTI-VARIANT INFERENCE MODELS

Non-Final OA §101§103
Filed
Mar 26, 2024
Examiner
VANWORMER, SKYLAR K
Art Unit
Tech Center
Assignee
Dell Products L.P.
OA Round
1 (Non-Final)
47%
Grant Probability
Moderate
1-2
OA Rounds
1y 8m
Est. Remaining
75%
With Interview

Examiner Intelligence

Grants 47% of resolved cases
47%
Career Allowance Rate
15 granted / 32 resolved
-13.1% vs TC avg
Strong +28% interview lift
Without
With
+28.1%
Interview Lift
resolved cases with interview
Typical timeline
4y 2m
Avg Prosecution
12 currently pending
Career history
64
Total Applications
across all art units

Statute-Specific Performance

§101
25.5%
-14.5% vs TC avg
§103
62.6%
+22.6% vs TC avg
§102
3.2%
-36.8% vs TC avg
§112
7.9%
-32.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 32 resolved cases

Office Action

§101 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 03/26/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-20 rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. An information handling system, comprising: a memory device to store code; and (Mere instruction to apply exception using generic computer components) a processor configured to execute code to: (Mere instruction to apply exception using generic computer components) define a first grouping of inputs to a first inference model; (Mental Process) determine a first number of inference stages for the first inference model; (Mental Process) calculate an accuracy of an output of the first inference model; (Mathematical Concept) compare the accuracy with a threshold accuracy; and (Mental Process) when the accuracy is within the threshold accuracy, load the first inference model to a plurality of computing devices (Mere instruction to apply the exception using generic computer components). The analysis for claims 11 and 20 is analogous to claim 1. The information handling system of claim 1, wherein, when the accuracy is not within the threshold accuracy the processor is further configured to: define a second grouping of the inputs to a second inference model; (Mental Process) determine a second number of inference stages for the second inference model; (Mental Process) calculate the accuracy of an output of the second inference model; (Mathematical Concept) compare the accuracy with the threshold accuracy; and (Mental Process) when the accuracy is within the threshold accuracy, load the second inference model to the plurality of computing devices. (Mere instruction to apply the exception using generic computer components). The analysis for claim 12 is analogous to claim 2. The information handling system of claim 1, wherein in defining the first grouping, the processor is further configured to (Mere instruction to apply exception using generic computer components) determine that the inputs in each of a sub-group of the first grouping are related inputs. (Mental Process) The analysis for claim 13 is analogous to claim 3. The information handling system of claim 3, wherein the related inputs include at least one of related application variable inputs, related hardware parameter inputs, and power range inputs. (Mental Process) The analysis for claim 14 is analogous to claim 4. The information handling system of claim 1, wherein in defining the first grouping, the processor is further configured to apply at least one of a Bayesian analysis, a conditional analysis, an absolute probability analysis, and a contingency grouping analysis to the inputs. (Mathematical Concept) The analysis for claim 15 is analogous to claim 5. 6. The information handling system of claim 1, wherein determining the first number of inference stages is based on the first grouping. (Mental Process) The analysis for claim 16 is analogous to claim 6. 7. The information handling system of claim 1, wherein the first number of inference stages is at least two inference stages. (Mental Process) The analysis for claim 17 is analogous to claim 7. 8. The information handling system of claim 1, wherein the first number of inference stages is not more than three inference stages. (Mental Process) The analysis for claim 18 is analogous to claim 8. 9. The information handling system of claim 1, wherein each of the first number of inference stages applies an artificial intelligence/machine learning (AI/ML) model. (Mere instruction to apply exception using generic computer components) 10. The information handling system of claim 8, wherein the AI/ML model includes at least one of a regression model, a decision tree model, a support vector means model, a Naïve Bayes model, a K-nearest neighbors model, a K-means model, a random forest model, a dimensional reduction model, and a gradient boosting model. (Mere instruction to apply exception using generic computer components) The analysis for claim 19 is analogous to claim 10. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-2, 4, 6-12, 14, 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Samuel et al (US Published Patent Application No. 20220342738, "Samuel"), in view of Shahid et al (US Published Patent Application No. 20230269143, "Shahid"). In regard to claim 1, Samuel teaches An information handling system, comprising: (Samuel, paragraph 0031, “The information handling system may include memory, one or more processing resources such as a central processing unit ("CPU"), microcontroller, or hardware or software control logic.”) a memory device to store code; and (Samuel, paragraph 0031, “The information handling system may include memory, one or more processing resources such as a central processing unit ("CPU"), microcontroller, or hardware or software control logic.”) a processor configured to execute code to: (Samuel, paragraph 0031, “The information handling system may include memory, one or more processing resources such as a central processing unit ("CPU"), microcontroller, or hardware or software control logic.”) define a first grouping of inputs to a first inference model; (Samuel, paragraph 0056, “The illustrated optimized diagnostic plan 141 illustrated in FIG. 5 is represented as a table comprised of a set of input attributes 261, depicted on the left side of the illustrated table, and inferred attributes 262 on the right side.”) However, Samuel does not explicitly teach determine a first number of inference stages for the first inference model; calculate an accuracy of an output of the first inference model; compare the accuracy with a threshold accuracy; and when the accuracy is within the threshold accuracy, load the first inference model to a plurality of computing devices. Shahid teaches determine a first number of inference stages for the first inference model; (Shahid, paragraph 0055, ““FIG. 2 is a flow diagram illustrating a process flow [determine a first number of inference stages] 30 of the computing system 10. In some embodiments, the process flow 30 may represent actions of the alarm prioritization unit 28 shown in FIG. 1. The process flow 30 includes an overall flow that starts with a data collection stage 32. For example, the data collection stage 32 may include a receiving step for obtaining freeform comments and freeform textual data from different sources. The data may be collected via the network 26 from equipment provided by different vendors.”) calculate an accuracy of an output of the first inference model; (Shahid, paragraph 0011, “The selected ML model may also be selected based on a) an historic accuracy score of each of the plurality of ML models calculated during training, b) an expected accuracy score of each of the plurality of ML models for later use during inference, c) a computational cost of each of the plurality of ML models during training, d) a training time associated with each of the plurality of ML models, and/or e) an estimated inference time associated with each of the plurality of ML models.”) compare the accuracy with a threshold accuracy; and (Shahid, paragraph 0125, “Also, a second (or additional) ML model(s) should be able to perform with sufficient accuracy after the dataset reaches a certain threshold (size) where it can at least closely match the accuracy of the first ML model.”) when the accuracy is within the threshold accuracy, load the first inference model to a plurality of computing devices. (Shahid, paragraph 0098, “Thresholds may be in place to determine switching from one model to another. Of course, the thresholds can be learned as well, since different systems can vary from one system to another. Detection of accuracy can also be automated. The computing system 10 can divide this into a training dataset and a testing dataset. The training dataset can be used to train or learn the function. Then, the testing dataset (which is kept separate) is fed to the model to see how accurate the predictions are from the true results.”) Samuel and Shahid are related to the same field of endeavor (i.e. information handling systems). In view of the teachings of Shahid, it would have been obvious for a person with ordinary skill in the art to apply the teachings of Shahid to Samuel before the effective filing date of the claimed invention in order to allow for greater accuracy and a faster training time. (Shahid, paragraph 0012, “For example, the first ML model may provide greater accuracy than the second ML model, and the second ML model may provide a faster training time and faster inference time than the first ML model.”) In regard to claim 11, the claim recites similar limitations as corresponding claim 1, and is rejected for similar reasons as claim 1 using similar teachings and rationale. In regard to claim 20, the claim recites similar limitations as corresponding claim 1, and is rejected for similar reasons as claim 1 using similar teachings and rationale. In regard to claim 2 and analogous claim 12, Samuel and Shahid teach the method of claim 1. Samuel further teaches define a second grouping of the inputs to a second inference model; (Samuel, paragraph 0056, “The illustrated optimized diagnostic plan 141 illustrated in FIG. 5 is represented as a table comprised of a set of input attributes 261, depicted on the left side of the illustrated table, and inferred attributes 262 on the right side.”) However, Samuel does not explicitly teach determine a second number of inference stages for the second inference model; calculate the accuracy of an output of the second inference model; compare the accuracy with the threshold accuracy; and when the accuracy is within the threshold accuracy, load the second inference model to the plurality of computing devices. Shahid teaches determine a second number of inference stages for the second inference model; (Shahid, paragraph 0055, ““FIG. 2 is a flow diagram illustrating a process flow 30 of the computing system 10. In some embodiments, the process flow 30 may represent actions of the alarm prioritization unit 28 shown in FIG. 1. The process flow 30 includes an overall flow that starts with a data collection stage 32. For example, the data collection stage 32 may include a receiving step for obtaining freeform comments and freeform textual data from different sources. The data may be collected via the network 26 from equipment provided by different vendors.”) calculate the accuracy of an output of the second inference model; (Shahid, paragraph 0011, “The selected ML model may also be selected based on a) an historic accuracy score of each of the plurality of ML models calculated during training, b) an expected accuracy score of each of the plurality of ML models for later use during inference, c) a computational cost of each of the plurality of ML models during training, d) a training time associated with each of the plurality of ML models, and/or e) an estimated inference time associated with each of the plurality of ML models.”) compare the accuracy with the threshold accuracy; and (Shahid, paragraph 0098, “Also, a second (or additional) ML model(s) should be able to perform with sufficient accuracy after the dataset reaches a certain threshold (size) where it can at least closely match the accuracy of the first ML model.”) when the accuracy is within the threshold accuracy, load the second inference model to the plurality of computing devices. (Shahid, paragraph 0098, “Also, a second (or additional) ML model(s) should be able to perform with sufficient accuracy after the dataset reaches a certain threshold (size) where it can at least closely match the accuracy of the first ML model.”) Samuel and Shahid are combinable for the same rationale as set forth above with respect to claim 1. In regard to claim 3 and analogous claim 13, Samuel and Shahid teach the method of claim 1. Samuel further teaches wherein in defining the first grouping, the processor is further configured to determine that the inputs in each of a sub-group of the first grouping are related inputs. (Samuel, paragraph 0020, “Technical advantages of the present disclosure may be readily apparent to one skilled in the art from the figures, description and claims included herein. The objects and advantages of the embodiments will be realized and achieved at least by the elements, features, and combinations particularly pointed out in the claims.”) In regard to claim 4 and analogous claim 14, Samuel and Shahid teach the method of claim 3. Samuel further teaches wherein the related inputs include at least one of related application variable inputs, related hardware parameter inputs, and power range inputs. (Samuel, paragraph 0049, “The five data collection parameters 124 illustrated in FIG. 3 include a memory health parameter, a hard drive health parameter, a graphics processing unit (GPU) health parameter, a central processing unit (CPU) health parameter, and a temperature parameter associated with a distressed GPU.”) In regard to claim 6 and analogous claim 16, Samuel and Shahid teach the method of claim 1. Shahid further teaches wherein determining the first number of inference stages is based on the first grouping. (Shahid, paragraph 0055, “FIG. 2 is a flow diagram illustrating a process flow 30 of the computing system 10. In some embodiments, the process flow 30 may represent actions of the alarm prioritization unit 28 shown in FIG. 1. The process flow 30 includes an overall flow that starts with a data collection stage 32. For example, the data collection stage 32 may include a receiving step for obtaining freeform comments and freeform textual data from different sources. The data may be collected via the network 26 from equipment provided by different vendors.”) Samuel and Shahid are combinable for the same rationale as set forth above with respect to claim 1. In regard to claim 7 and analogous claim 17, Samuel and Shahid teach the system of claim 1. Shahid further teaches wherein the first number of inference stages is at least two inference stages. (Shahid, paragraph 0055, “FIG. 2 is a flow diagram illustrating a process flow 30 of the computing system 10. In some embodiments, the process flow 30 may represent actions of the alarm prioritization unit 28 shown in FIG. 1. The process flow 30 includes an overall flow that starts with a data collection stage 32. For example, the data collection stage 32 may include a receiving step for obtaining freeform comments and freeform textual data from different sources. The data may be collected via the network 26 from equipment provided by different vendors.”) Samuel and Shahid are combinable for the same rationale as set forth above with respect to claim 1. In regard to claim 8 and analogous claim 18, Samuel and Shahid teach the system of claim 1. Shahid further teaches wherein the first number of inference stages is not more than three inference stages. (Shahid, paragraph 0055, “FIG. 2 is a flow diagram illustrating a process flow 30 of the computing system 10. In some embodiments, the process flow 30 may represent actions of the alarm prioritization unit 28 shown in FIG. 1. The process flow 30 includes an overall flow that starts with a data collection stage 32. For example, the data collection stage 32 may include a receiving step for obtaining freeform comments and freeform textual data from different sources. The data may be collected via the network 26 from equipment provided by different vendors.”) Samuel and Shahid are combinable for the same rationale as set forth above with respect to claim 1. In regard to claim 9, Samuel and Shahid teach the system of claim 1. Shahid further teaches wherein each of the first number of inference stages applies an artificial intelligence/machine learning (AI/ML) model. (Shahid, paragraph 0030, “The present disclosure relates to systems and methods for handling faults, alarms, and other issues in a system, such as communications or telecommunications system or network. According to various embodiments, the systems and methods described herein are configured to utilize multiple Machine Leaming (ML) models (e.g., ML processes, techniques, algorithms, etc.). For example, a first ML model may be used at an early stage, such as when a network is first deployed or when the network is modified and reset whereby only new information about the network is relevant. At this early stage, a high performing ML model (e.g., a Neural Network (NN), Siamese NN (SNN), or other type of model) may be used, even when little data is available.”) Samuel and Shahid are combinable for the same rationale as set forth above with respect to claim 1. In regard to claim 10 and analogous claim 19, Samuel and Shahid teach the system of claim 8. Shahid further teaches wherein the AI/ML model includes at least one of a regression model, a decision tree model, a support vector means model, a Naïve Bayes model, a K-nearest neighbors model, a K-means model, a random forest model, a dimensional reduction model, and a gradient boosting model. (Shahid, paragraph 0030, “The present disclosure relates to systems and methods for handling faults, alarms, and other issues in a system, such as communications or telecommunications system or network. According to various embodiments, the systems and methods described herein are configured to utilize multiple Machine Leaming (ML) models (e.g., ML processes, techniques, algorithms, etc.). For example, a first ML model may be used at an early stage, such as when a network is first deployed or when the network is modified and reset whereby only new information about the network is relevant. At this early stage, a high performing ML model (e.g., a Neural Network (NN), Siamese NN (SNN), or other type of model) may be used, even when little data is available.”) Samuel and Shahid are combinable for the same rationale as set forth above with respect to claim 1. Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Samuel, in view of Shahid and in further view of Guzik et al (US Published Patent Application No. 20220172087, "Guzik"). In regard to claim 5 and analogous claim 15, Samuel and Shahid teach the system of claim 1. However, Samuel and Shahid do not explicitly teach wherein in defining the first grouping, the processor is further configured to apply at least one of a Bayesian analysis, a conditional analysis, an absolute probability analysis, and a contingency grouping analysis to the inputs. Guzik teaches wherein in defining the first grouping, the processor is further configured to apply at least one of a Bayesian analysis, a conditional analysis, an absolute probability analysis, and a contingency grouping analysis to the inputs. (Guzik, paragraph 0032, “The machine learning function 222 may use machine learning algorithms to generate a second set of predictions 130 and an associated second margin of error 132. Various classification schemes ( explicitly and/or implicitly trained) and/or systems may be employed by the machine learning function 216 for the generation of a second set of results and associated margin of error, such as a probabilistic and/or a statistical based analysis.”) Samuel, Shahid and Guzik are related to the same field of endeavor (i.e. information handling systems). In view of the teachings of Guzik, it would have been obvious for a person with ordinary skill in the art to apply the teachings of Guzik to Samuel and Shahid before the effective filing date of the claimed invention in order to predict accurate outcomes. (Guzik, paragraph 0002, “As a result, a machine learning algorithm's effectiveness to predict accurate outcomes is dependent on the quality of the input or training data.”) Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SKYLAR K VANWORMER whose telephone number is (703)756-1571. The examiner can normally be reached M-F 6:00am to 3:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Usmaan Saeed can be reached at (571) 272-4046. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /S.K.V./Examiner, Art Unit 2146 /SHAHID K KHAN/Primary Examiner, Art Unit 2146
Read full office action

Prosecution Timeline

Mar 26, 2024
Application Filed
Aug 26, 2026
Non-Final Rejection mailed — §101, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
47%
Grant Probability
75%
With Interview (+28.1%)
4y 2m (~1y 8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 32 resolved cases by this examiner. Grant probability derived from career allowance rate.

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