Prosecution Insights
Last updated: July 17, 2026
Application No. 18/616,911

SUSPENSION REGION CONFIGURATION FOR SEMICONDUCTOR DEVICES

Non-Final OA §102§112
Filed
Mar 26, 2024
Examiner
SOWARD, IDA M
Art Unit
Tech Center
Assignee
International Business Machines Corporation
OA Round
1 (Non-Final)
93%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
1260 granted / 1351 resolved
+33.3% vs TC avg
Moderate +6% lift
Without
With
+5.5%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
53 currently pending
Career history
1383
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
48.0%
+8.0% vs TC avg
§102
29.0%
-11.0% vs TC avg
§112
22.0%
-18.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1351 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action is in response to the election filed June 4, 2026. Election/Restrictions Applicant’s election without traverse of claims 1-17 in the reply filed on June 4, 2026 is acknowledged. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the curved-shaped inner spacer structures must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. The drawings are objected to because there is no reference character for the interlayer dielectric layer. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The abstract of the disclosure is objected to because “comprising” should have been including in line 2. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b). The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: SEMICONDUCTOR DEVICE INCLUDING CURVED-SHAPED INNER SPACER STRUCTURES. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In regard to claim 1, what elements specifically constitutes the first and second stacked transistor structures? Also, it is not understood what actually constitutes the curved-shaped inner spacer structure? A curve is a continuously bending line or path without angles. Claims 2-10 are rejected as being dependent upon rejected claim 1. In regard to claim 11, what elements specifically constitutes the first, second and third stacked transistor structures? Also, it is not understood what actually constitutes the curved-shaped inner spacer structure? A curve is a continuously bending line or path without angles. Claims 12-17 are rejected as being dependent upon rejected claim 11. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 4 and 10-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 2022/0352326 A1). In regard to claim 1, Huang et al. teach a semiconductor device 500 comprising: a first stacked transistor structure (left structure) and a second stacked transistor structure (center structure) disposed above an interlayer dielectric layer 260, each comprising a plurality of channel layers 208 alternately stacked with a plurality of gate regions 213’; a first source/drain region 205S/D that contacts the plurality of channel layers 208 of the first stacked transistor structure (left structure) and the second stacked transistor structure (center structure), wherein at least a portion of the first source/drain region 205S/D that is above the interlayer dielectric layer 260 and below a first channel layer 208 of the plurality of channel layers 208 is disposed between curved-shaped inner spacer structures 220 of the first stacked transistor structure (left structure) and the second stacked transistor structure (center structure); and a first source/drain contact 248 connected to the first source/drain region 205S/D (Figures 2, 30 and 39, pages 2-9, paragraphs [0020]-[0059]). In regard to claim 4, Huang et al. teach the interlayer dielectric layer 260 and the first channel layer 208 of the plurality of channel layers 208 are spaced apart from each other at a first distance and at least two consecutive channel layers 208 of the plurality of channel layers 208 spaced apart from each other at a second distance that is different than the first distance (Figures 2, 30 and 39, pages 2-9, paragraphs [0020]-[0059]). In regard to claim 10, Huang et al. teach a second source/drain region 205S/D that contacts the plurality of channel layers 208 of the second stacked transistor structure (center structure); and a second source/drain contact 248 disposed beneath the second source/drain region 205S/D, wherein a portion of the second source/drain contact 248 extends above the interlayer dielectric layer 260 and below the first channel layer 208 (Figures 2, 30 and 39, pages 2-9, paragraphs [0020]-[0059]). In regard to claim 11, Huang et al teach a semiconductor device 500 comprising: a first source/drain region 205S/D that contacts channel layers 208 of a first stacked transistor structure (left structure) and a second stacked transistor structure (center structure); a second source/drain region (center structure) that contacts channel layers 208 of the second stacked transistor structure (center structure) and a third stacked transistor structure (right structure); and a backside source/drain contact 268 connected to the second source/drain region 205S/D; wherein a bottom portion of the first source/drain region 205S/D is disposed between a first curved-shaped inner spacer structure 220 of the first stacked transistor structure (left structure) and a second curved-shaped inner spacer structure 220 of the second stacked transistor structure (center structure), and wherein the backside source/drain contact 268 is disposed between a third curved-shaped inner spacer structure 220 of the second stacked transistor structure (center structure) and a fourth curved-shaped inner spacer structure 220 of the third stacked transistor structure (right structure) (Figures 3 2, 30 and 39, pages 2-9, paragraphs [0020]-[0059]). Allowable Subject Matter Claims 2, 5, 12 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 3 is objected to as being dependent upon objected claim 2. Claims 6-9 are objected to as being dependent upon objected claim 5. Claims 13-16 are objected to as being dependent upon objected claim 12. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to semiconductor devices: Huang et al. (US 2022/0238660 A1) Huang et al. (US 2022/0310455 A1) More et al. (US 2021/0391450 A1) Wong et al. (US 2022/0328648 A1) Yi et al. (US 2020/0395446 A1). Any inquiry concerning this communication or earlier communications from the examiner should be directed to IDA M SOWARD whose telephone number is (571)272-1845. The examiner can normally be reached Monday through Thursday, 7am to 5:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. IMS June 29, 2026 /IDA M SOWARD/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Mar 26, 2024
Application Filed
Jul 02, 2026
Non-Final Rejection mailed — §102, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
93%
Grant Probability
99%
With Interview (+5.5%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1351 resolved cases by this examiner. Grant probability derived from career allowance rate.

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