DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 10/20/2025 is acknowledged.
Claims 9-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/20/2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 recites the limitation "the inflection point" of claim 1. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6, and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by FUKUNAGA et al (US 2020/0066446).
Regarding claim 1, FUKUNAGA discloses a ceramic electronic device (Fig. 1-10) comprising: a multilayer chip (Fig. 2, 10) having a multilayer portion (Fig. 6, 60) in which each of a plurality of dielectric layers (Fig. 2, 12) and each of a plurality of internal electrode layers (Fig. 2, 13) are alternately stacked, wherein the plurality of internal electrode layers are extracted alternately to two end faces (Fig. 2, 15a/b) of the multilayer chip facing each other (Fig. 2), wherein the multilayer chip has a side margin (Fig. 3, 23) outside a capacity section in which the plurality of dielectric layers and the plurality of internal electrode layers face each other (Fig. 3), in a third direction (Fig. 1, W) orthogonal to a first direction (Fig. 1, T) in which the plurality of internal electrode layers face each other and a second direction (Fig. 1, L) in which the two end faces face each other (Fig. 1), wherein the multilayer chip has cover layers (Fig. 3, 22) of which a main component is ceramic ([0051]), on an upper face and a lower face of the capacity section in the first direction (Fig. 2), wherein each of the side margin and the cover layers has, on a side of an outer surface, a high concentration portion (Fig. 3, 23a/22a) of a subcomponent of at least one of Si ([0052/0065]), Mn, Cu, Fe, V, Ni, B, Mg, Ho, Dy, Er, Tm, Yb, Gd, Li, Co, Sm and Y, and wherein a concentration of the subcomponent of the high concentration portion is higher than that of a portion closer to the capacity section than the high concentration portion ([0052/0065]).
Regarding claim 6, FUKUNAGA further discloses that, in the high concentration portion, the subcomponent exists in a form of a single element (Si [0052-0053]), an oxide crystal, or glass.
Regarding claim 8, FUKUNAGA discloses a ceramic electronic device (Fig. 1-10) comprising: a multilayer chip (Fig. 2, 10) having a multilayer portion (Fig. 6, 60) in which each of a plurality of dielectric layers (Fig. 2, 12) and each of a plurality of internal electrode layers (Fig. 2, 13) are alternately stacked, wherein the plurality of internal electrode layers are extracted alternately to two end faces (Fig. 2, 15a/b) of the multilayer chip facing each other (Fig. 2), wherein the multilayer chip has a side margin (Fig. 3, 23) outside a capacity section in which the plurality of dielectric layers and the plurality of internal electrode layers face each other (Fig. 3), in a third direction (Fig. 1, W) orthogonal to a first direction (Fig. 1, T) in which the plurality of internal electrode layers face each other and a second direction (Fig. 1, L) in which the two end faces face each other (Fig. 1), wherein the multilayer chip has cover layers (Fig. 3, 22) of which a main component is ceramic ([0051]), on an upper face and a lower face of the capacity section in the first direction (Fig. 2), wherein each of the side margin and the cover layers has, on a side of an outer surface, a high concentration portion (Fig. 3, 23a/22a) of a subcomponent of at least one of Si ([0052/0065]), Mn, Cu, Fe, V, Ni, B, Mg, Ho, Dy, Er, Tm, Yb, Gd, Li, Co, Sm and Y, wherein a concentration of the subcomponent of the high concentration portion is higher than that of a portion closer to the capacity section than the high concentration portion ([0052/0065]), and wherein the high concentration portion is located within a range of 5.2% to 76% from the outer surface with respect to a thinner one of a thickness of the side margin and a thickness of the cover layers (Fig. 3, at least some of the high concentration region is in that range).
Allowable Subject Matter
Claims 2, 4-5, and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, 4-5, and 7, the prior art fails to teach or make obvious, alone or in combination, the limitation of “wherein the high concentration portion is a portion from an inflection point of the concentration of the subcomponent to the outer surface, and wherein the inflection point is a point that satisfies dD/dd ≥ 35 when a normalized intensity (D (%)) normalized by setting intensity to intensity/maximum intensity × 100 and a distance from the capacity section to the outer surface is d (μm) when acquiring an EPMA line spectrum from the capacity section to the outer surface” in combination with the other claim limitations.
Additional Relevant Prior Art:
TANAKA et al (US 2017/0018363) teaches relevant art in Fig. 1-10.
Mizuno et al (US 2017/0243697) teaches relevant art in Fig. 1-4.
Kowase (US 2018/0182555) teaches relevant art in Fig. 1-4.
SAKATE et al (US 2018/0261389) teaches relevant art in Fig. 1-4.
LEE et al (US 2020/0402717) teaches relevant art in Fig. 1-6.
MIZUNO (US 2022/0285100) teaches relevant art in Fig. 1-8.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL P MCFADDEN whose telephone number is (571)270-5649. The examiner can normally be reached M-Thur 8am-9pm PST.
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/MICHAEL P MCFADDEN/Primary Examiner, Art Unit 2848