Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-5,7-8,10-14,16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (PG Pub 2005/0263801 A1) and Hiyama et al (PG Pub 2004/0007765 A1).
Regarding claim 1, Park teaches a memory cell comprising: a conductive via (35, figs. 12-15) coupled to the stack; a stack of layers coupled to the conductive via, the stack of layers including; a layer made of a phase-change material (chalcogenide 37a, paragraph [0053]); a first electrode (39a, paragraph [0053]) on the layer made of the phase-change material; and a protection layer (43) on the first electrode; and an encapsulation layer made of a silicon nitride (48, paragraph [0056]), the protection layer being between the encapsulation layer and the first electrode.
Park does not teach the silicon nitride to have a density smaller than 2.2 g/cm3. Park also does not teach the material of the interlayer dielectric 49.
In the same field of endeavor, Hiyama teaches a silicon nitride layer (23, fig. 2) a density smaller than 2.2 g/cm3 (abstract), for the benefit of preventing voids being formed in oxide layer 24 (paragraphs [0035][0038]). Hiyama teaches O3/TEOS to form the oxide layer to achieve the benefit of excellent gap filling characteristic (paragraph [0004])
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make the interlayer dielectric 49 an oxide layer in Park, for the benefit of providing a layer with excellent gap filling ability, and to make the silicon nitride in Park to have a density smaller than 2.2 g/cm3, for the benefit of preventing voids being formed in oxide layer 49.
Regarding claim 2, Park teaches the memory cell according to claim 1, wherein the encapsulation layer covers sides of the layer made of the phase-change material and of the first electrode (fig. 14).
Regarding claim 3, Hiyama teaches the memory cell according to claim 1, wherein the encapsulation layer has a density smaller than 2.15 g/cm3 (fig. 8).
Regarding claim 4, Park teaches the memory cell according to claim 1, wherein the phase-change material is a chalcogenide (paragraph [0054]).
Regarding claim 5, Park teaches the memory cell according to claim 4, wherein the phase-change material is an alloy of germanium, antimony, and tellurium (GeSbTe, paragraph [0054]).
Regarding claim 7, Park teaches the memory cell according to claim 1, wherein the encapsulation layer has a thickness in the range from 5 nm to 80 nm (samples C and D, 200 angstroms, paragraph [0081]).
Regarding claim 8, Park in view of Hiyama (see claim 1) a method of manufacturing a memory cell comprising: forming a conductive via; forming a stack of layers coupled to the conductive via, the stack of layers including a layer of a phase-change material, a first electrode on the layer of the phase-change material, and a protection layer on the first electrode; and forming an encapsulation layer made of a silicon nitride having a density smaller than 2.2 g/cm3.
Regarding claim 10, Park in view of Hiyama (see claim 1) a device, comprising: an integrated memory circuit that includes: a plurality of memory cells, wherein each memory cell includes a stack of layers and a conductive via coupled to the stack of layers, the stack of layers including: a layer made of a phase-change material; a first electrode; a protection layer on the first electrode; and an encapsulation layer made of a silicon nitride having a density smaller than 2.2 g/cm3, the protection layer being between the first electrode and the encapsulation layer.
Regarding claim 11, Park teaches the device of claim 10, wherein the encapsulation layer covers sides of the layer made of the phase-change material and of the first electrode (fig. 14).
Regarding claim 12, Hiyama teaches the device of claim 10, wherein the encapsulation layer has a density smaller than 2.15 g/cm3 (fig. 8).
Regarding claim 13, Park teaches the device of claim 10, wherein the phase-change material is a chalcogenide (paragraph {0054]).
Regarding claim 14, Park teaches the device of claim 13, wherein the phase-change material is an alloy of germanium, antimony, and tellurium (GeSbTe, paragraph [0054]).
Regarding claim 16, Park teaches the device of claim 10, wherein the encapsulation layer has a thickness in the range from 5 nm to 80 nm (samples C and D, 200 angstroms, paragraph [0081]).
Claim(s) 6 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (PG Pub 2005/0263801 A1) and Hiyama et al (PG Pub 2004/0007765 A1) as applied to claims 1 and 10 above, and further in view of Choi et al (PG Pub 2010/0301480 A1).
Regarding claim 6, the previous combination remains as applied in claim 1.
Park does not teach a heating element.
In the same field of endeavor, Choi teaches between the layer made of the phase-change material (514, fig. 11) and the first electrode (506/508), a heating element (510, paragraph [0180]) surrounded with an insulating layer (512, paragraph [0181]), for the benefit of achieving reduced set/reset current (paragraphs [0183] to [0188]).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include, between the layer made of the phase-change material and the first electrode, a heating element surrounded with an insulating layer, for the benefit of achieving reduced set/reset current.
Regarding claim 15, the previous combination remains as applied in claim 10.
Park does not teach a heating element.
In the same field of endeavor, Choi teaches between the layer made of the phase-change material (514, fig. 11) and the first electrode (506/508), a heating element (510, paragraph [0180]) surrounded with an insulating layer (512, paragraph [0181]), for the benefit of achieving reduced set/reset current (paragraphs [0183] to [0188]).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include, between the layer made of the phase-change material and the first electrode, a heating element surrounded with an insulating layer, for the benefit of achieving reduced set/reset current.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (PG Pub 2005/0263801 A1) and Hiyama et al (PG Pub 2004/0007765 A1) as applied to claims 1 and 4 above, and further in view of Hansen et al (US Patent 10,147,875 B1).
Regarding claim 9, the previous combination remains as applied in claim 1.
Park further teaches the deposition of the encapsulation layer is performed by plasma enhanced chemical vapor deposition (paragraph [0056]).
Park does not teach the deposition of the encapsulation layer is performed by pulsed plasma enhanced chemical vapor deposition.
In the same field of endeavor, Hansen teaches the deposition of the encapsulation layer (silicon nitride 106, fig. 1A) is performed by pulsed plasma enhanced chemical vapor deposition (column 10, lines 37-45), for the benefit of enabling deposition in low-temperature (column 10, lines 37-45).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to perform the deposition of the encapsulation layer by pulsed plasma enhanced chemical vapor deposition for the benefit of enabling deposition in low-temperature.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEIFEI YEUNG LOPEZ whose telephone number is (571)270-1882. The examiner can normally be reached M-F: 8am to 4pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571 270 7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899
Prosecution Insights