Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This action is in response to the amendment filed on 12/29/2025. Claims 1-20 have been cancelled while claims 21-40 have been added. Claims 21-40 remain rejected in the application.
Response to Arguments
There are no arguments to address. However, applicant noted “As discussed during the Examiner Interview, the cited references, alone or in combination, do not teach or suggest "an integrated-circuit package coupled to the frame of the pair of artificial-reality glasses, the integrated-circuit package comprising ... the artificial-reality task-specific chiplet [] configured to generate the artificial-reality output by performing one or more artificial-reality processing tasks based on data from the one or more body-tracking sensors," as recited by independent claim 21. ”. Examiner notes that in the interview conducted on 12/29/2025, the only agreement made was the proposed amendment overcomes the current rejection at the time which was a 102, which is now a 103. However, Examiner never suggested that the references in combination fail to teach the proposed amendment. Claims 21-40 remain rejected in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21, 22, 23, 24, 25, 26, 29, 30, 31, 32, 33, 35, 37, 38, and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Matam et. al (U.S. Patent Publication No. 2021/0133913), in view of Snyder et al. (WO 2022/132960), in further view of Foo et. al (U.S. Patent Publication No. 2019/0304876).
Regarding claim 21, Matam discloses a pair of artificial-reality glasses comprising [Matam: 0223 “augmented reality ( AR ) or virtual reality ( VR )”](teaches AR and VR which are both artificial reality systems): the integrated-circuit package comprising: a system-on-chip having a first die-to-die interface (interpreted as the package includes a general purpose SoC with a die-to-die meaning an interface used to connect separate dies inside a package) [Matam: 0396 “general - purpose graphics processor comprising a base die”], wherein the system-on-chip is configured to present, via the display device, an artificial reality to a user of the pair of artificial- reality glasses based on an artificial-reality output of an artificial-reality task-specific chiplet (interpreted as the system on chip drives the display to present AR using the task chiplets output)[Matam: 0223 “smart eyewear or clothing enhanced with augmented reality ( AR ) or virtual reality ( VR ) features to provide visual , audio or tactile outputs to supplement real world visual , audio or tactile experiences or otherwise provide text , audio , graphics , video , holographic images or video , or tactile feedback ; other augmented reality ( AR ) device ; or other virtual reality ( VR ) device . In some embodiments , the processing system 1400 includes or is part of a television or set top box device”][Matam: 0243 “graphics processor 1600 also includes a display controller 1602 to drive display output data to a display device 1618. Display controller 1602 includes hardware for one or more overlay planes for the display and composition of multiple layers of video or user interface elements. The display device 1618 can be an internal or external display device. In one embodiment the display device 1618 is a head mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device.”](teaches including a display controller that composes multiple layers and drives a HMD AR display); and the artificial-reality task-specific chiplet having a second die-to-die interface, wherein the artificial-reality task-specific chiplet is configured to generate the artificial-reality output by performing one or more artificial-reality processing tasks based on data from the one or more body-tracking sensors (same cited quote/reference as above), but fails to explicitly disclose a display device coupled to a lens of the pair of artificial-reality glasses; one or more body-tracking sensors coupled to a frame of the pair of artificial-reality glasses; and an integrated-circuit package coupled to the frame of the pair of artificial-reality glasses, and a redistribution layer coupling the second die-to-die interface to the first die-to-die interface of the system-on-chip.
However, Snyder discloses a display device coupled to a lens of the pair of artificial-reality glasses [Snyder: 0048 “HMD may impact a quality of images presented in virtual reality (VR) and/or augmented reality (AR)”][Snyder: 0049 “the HMD according to the instant application may take many forms, including helmets, visors, goggles, masks, glasses”](explicitly teaches AR HMD glasses); one or more body-tracking sensors coupled to a frame of the pair of artificial-reality glasses [Snyder: 0070 “in addition to including one or more displays, the display housing 108 may include battery(ies), sensor(s) adjustment mechanism(s), button(s), interface(s), controller(s), module(s), and so forth so carrying out an operation of the HMD 100”](explicitly teaches sensors used for the HMD (interpreted as glasses)); and an integrated-circuit package coupled to the frame of the pair of artificial-reality glasses [Snyder: 0068 “the HMD may include a flexible printed circuit”].
However, Foo discloses and a redistribution layer coupling the second die-to-die interface to the first die-to-die interface of the system-on-chip [Foo: 0022 “The two semiconductor waters 101 and 102 have each been assembled to respective redistribution layers 134 and 136 .”](teaches utilizing redistribution layers).
Matam, Snyder, and Foo are considered analogous to the claimed invention because they are in the same field of chiplet based SoC packaging used in AR/VR class processors. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Matam to incorporate Snyder’s and Foo’s teachings of utilizing AR glasses and redistribution layers. The motivation for such a combination would provide the benefit of improved user usability and fan-out and routing density, reduced resistance/inductance, and a lower profile interconnect path for high bandwidth links.
Regarding claim 22, Matam, Snyder, and Foo disclose the pair of artificial-reality glasses of claim 21, wherein the one or more artificial- reality processing tasks comprise a deep-learning operation (interpreted as the AR tasks utilizes deep learning)[Matam: 0101 “deep learning implementations”].
Regarding claim 23, Matam, Snyder, and Foo disclose the pair of artificial-reality glasses of claim 21, wherein the one or more artificial- reality processing tasks comprise a computer-vision operation [Matam: 0218 “computer vision operations”].
Regarding claim 24, Matam and Snyder disclose the pair of artificial-reality glasses of claim 21, but fail to explicitly disclose wherein: the system-on-chip comprises an active frontside having first active circuitry; the artificial-reality task-specific chiplet comprises an active frontside having second active circuitry; the active frontside of the system-on-chip faces a first direction; and the active frontside of the artificial-reality task-specific chiplet faces a second direction opposite the first direction.
However, Foo discloses wherein: the system-on-chip comprises an active frontside having first active circuitry (interpreted as the SoC has an active frontside (active surface) that contains devices and metal interconnect)[Foo: 0020 “The first semiconductive device 110 includes an active surface 114 and a backside surface 116 . The active surface 114 includes active devices and metallization 118”](teaches the active frontside and states it includes active devices and metallization); the artificial-reality task-specific chiplet comprises an active frontside having second active circuitry (interpreted as the separate task specific chiplet has its own active frontside with devices)[Foo: 0030 “Attention is directed to the subsequent die 148 , which includes an active surface 154 and a backside surface 156 . The active surface 154 includes active devices and metallization 158 ( hereinafter metallization 158 ) .”](teaches the subsequent die 148 which is a separate die mounted within the package which corresponds to the specific chiplet, further teaches it has an active surface with active devices and metallization); the active frontside of the system-on-chip faces a first direction; and the active frontside of the artificial-reality task-specific chiplet faces a second direction opposite the first direction [Foo: 0021 “The two wafers 101 and 102 are assembled face - to - face with respective adhesives 128 and 130 , which are bonded to a medium such as polymer media 132 that acts as a carrier .”][Foo: 0031 “The subsequent die 148 and the second die 150 are each mounted F2F with the first die 110”](teaches face to face, so their facing direction are opposites which are 2 separate directions and applying that direction to the chip is an obvious limitation).
Matam, Snyder, and Foo are considered analogous to the claimed invention because they are in the same field of chiplet based SoC packaging used in AR/VR class processors. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Matam and Snyder to incorporate Foo’s teachings of face-to-face mounting with active device surfaces oriented in opposite directions. The motivation for such a combination would provide the benefit of improving performance by having shorter die-to-die links a higher speed signal transmission for low latency interconnect.
Claim 25 corresponds to claim 24 with the only difference being, instead of system chips facing opposite sides, they face the same side which is an obvious implementation and a mere preference. Thus, claim 25 is rejected for the same reasons as claim 24 above.
Regarding claim 26, Matam, Snyder, and Foo disclose the pair of artificial-reality glasses of claim 21, wherein: the integrated-circuit package further comprises an interposer; and the system-on-chip and the artificial-reality task-specific chiplet are coupled together via the interposer [Matam: 0332 “Additionally the chiplets can be integrated into a base die or base chiplet using active interposer technology”].
Regarding claim 29, Matam, Snyder, and Foo disclose the pair of artificial-reality glasses of claim 21, wherein the body-tracking sensors comprise hand-tracking sensors (Matam: 1425; 1443; Fig. 14)(teaches touch sensors as well as keyboard/mouse which are real world body tracking sensors).
Regarding claim 30, Matam and Snyder disclose the pair of artificial-reality glasses of claim 21, but fail to explicitly disclose wherein the one or more artificial- reality processing tasks comprise an artificial-intelligence-assistant task.
However, Foo discloses wherein the one or more artificial- reality processing tasks comprise an artificial-intelligence-assistant task [Foo: 0060 “In an embodiment , a system 500 includes , but is not limited to a personal digital assistant ( PDA)”].
Matam, Snyder, and Foo are considered analogous to the claimed invention because they are in the same field of chiplet based SoC packaging used in AR/VR class processors. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Matam and Snyder to incorporate Foo’s teachings of utilizing a digital assistant. The motivation for such a combination would provide the benefit of improving user experience.
Claims 31 and 37 are method and non-transitory computer readable storage claims corresponding to claim 21 without any additional limitations. Thus, claims 31 and 37 are rejected for the same reasons as claim 21 above.
Claims 32 and 38 are method and non-transitory computer readable storage claims corresponding to claim 22 without any additional limitations. Thus, claims 32 and 38 are rejected for the same reasons as claim 22 above.
Claims 33 and 39 are method and non-transitory computer readable storage claims corresponding to claim 23 without any additional limitations. Thus, claims 33 and 39 are rejected for the same reasons as claim 23 above.
Claim 35 is a method claim corresponding to claim 29 without any additional limitations. Thus, claim 35 is rejected for the same reasons as claim 29 above.
Claims 27 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Matam et. al (U.S. Patent Publication No. 2021/0133913), in view of Snyder et al. (WO 2022/132960), in view of Foo et. al (U.S. Patent Publication No. 2019/0304876), in further view of Sharma et al. (U.S. Patent Publication No. 2022/0327084).
Regarding claim 27, Matam, Snyder, and Foo disclose the pair of artificial-reality glasses of claim 21, but fail to explicitly disclose wherein the first die-to-die interface of the system-on-chip and the second die-to-die interface of the artificial-reality task- specific chiplet are universal chiplet interconnects.
However, Sharma discloses wherein the first die-to-die interface of the system-on-chip and the second die-to-die interface of the artificial-reality task- specific chiplet are universal chiplet interconnects (interpreted as both D2D interfaces conform to the UCI standard) [Sharma: 0060 “An improved interconnect architecture is introduced herein to implement a standardized die - to - die inter face through the Universal Chiplet Interconnect Express ( UCIe ) protocol. Not only does UCIe enable a solution for general - purpose die - to - die interconnects for the on - package and off - package coupling of dies , but the standardization of the interface enable the interconnection of different devices from different vendors and different fabs across different technology nodes using different packaging choices to improve upon existing computing system and implement new systems.”].
Matam, Snyder, Foo and Sharma are considered analogous to the claimed invention because they address multi-chip packages with die-to-die links. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Matam, Snyder, and Foo to incorporate Sharma’s teachings of implementing interconnects. The motivation for such a combination would provide the benefit of a high bandwidth and low latency D2D protocol enabling multi-vendor chiplets and design reuse.
Claim 36 is a method claim corresponding to claim 27 without any additional limitations. Thus, claim 36 is rejected for the same reasons as claim 27 above.
Claims 28, 34, and 40 are rejected under 35 U.S.C. 103 as being unpatentable over Matam et al. (U.S. Patent Publication No. 2021/0133913), in view of Snyder et al. (WO 2022/132960), in view of Foo et al. (U.S. Patent Publication No. 2019/0304876), in further view of Schoen (U.S. Patent Publication No. 2022/0129082).
Regarding claim 28, Matam, Snyder, and Foo disclose the pair of artificial-reality glasses of claim 21, but fail to explicitly disclose wherein the body-tracking sensors comprise eye-tracking sensors.
However, Schoen discloses wherein the body-tracking sensors comprise eye-tracking sensors [Schoen: 0071 “Artificial reality glasses 1002 include eye tracking module 1006”].
Matam, Snyder, Foo and Schoen are considered analogous to the claimed invention because they address multi-chip packages with die-to-die links. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Matam, Snyder, and Foo to incorporate Schoen’s teachings of implementing an eye tracking module. The motivation for such a combination would provide the benefit of improved user experience.
Claims 34 and 40 are method and non-transitory computer readable storage claims corresponding to claim 28 without any additional limitations. Thus, claims 34 and 40 are rejected for the same reasons as claim 28 above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to AHMED TAHA whose telephone number is (571)272-6805. The examiner can normally be reached 8:30 am - 5 pm, Mon - Fri. Examiner interviews are available via telephone, in person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, XIAO WU can be reached at (571)272-7761. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786- 9199 (IN USA OR CANADA) or 571-272-1000.
/AHMED TAHA/Examiner, Art Unit 2613
/XIAO M WU/Supervisory Patent Examiner, Art Unit 2613
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