DETAILED ACTION
This office action is in response to the amendment filed on 04/30/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Response to Arguments
Applicant’s arguments with respect to the claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 26-28 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhao US 2021/0211052.
Regarding Claim 26, Zhao teaches (Figures 3-7 and 12) An apparatus (300) comprising: a power converter (buck converter) having a power input and a power output (at Vin and Vout); an amplifier (102) having a first input, a second input, and an output, the first input coupled to the power output (at 118), and the second input coupled to a reference input (Vref); and a control circuit (controller of 300 without 102) having a first input (at 124), a second input (at 302), and control outputs (at 114), and the first input coupled to the output of the amplifier (at 124), the second input coupled to the power input (at 302), the control circuit configurable to provide control signals (from 114) responsive to states of the first and second input to control transfer of power from the power input to the power output (control of the buck converter). (For Example: Par. 29-34)
Regarding Claim 27, Zhao teaches (Figures 3-7 and 12) further comprising a power stage (s1-s2) coupled between the power input and the power output (Vin and Vout), the power stage having control inputs coupled to the control outputs (at S1-s2). (For Example: Par. 29-34)
Regarding Claim 28, Zhao teaches (Figures 3-7 and 12) further comprising an inductor (Lout) coupled between the power input and the power stage or between the power stage (at 116) and the power output (at Vout).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhao US 2021/0211052 in view of Mednik US 2022/0200453.
Regarding Claim 1, Zhao teaches (Figures 3-7 and 12) a control circuit (controller of 100) comprising: a voltage control loop (with 102) configurable to produce a control voltage (at 124) based on a first voltage (at vfb) at an output of a DC-DC converter (buck) and a reference voltage (Vref); and a current control loop (with 302 and 104-106) configurable to produce a control current (from 104) based on the control voltage (from 102), and to adjust the control current (with 106) based on a signal proportional to a second voltage (Ipsm from 302) of an input of the DC-DC Converter (Vin), and to produce, based on the adjusted control current (from 106 ) and an inductor current (inductor current) in an inductor (Lout) of the DC-DC converter, a drive signal (from 114) to drive one or more power transistors (s1-s2) of the DC-DC converter to transfer power from the input to the output of the DC-DC converter (from Vin to Vout). (For Example: Par. 29-34)
Zhao does not teach provide an adjusted control current that is inversely proportional to the second voltage.
Mednik teaches (Figure 3) to provide an adjusted control current (from 118) that is inversely proportional to the second voltage (AxB/C, C is the input signal). (For Example: Par. 38-44)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Zhao to include to provide an adjusted control current that is inversely proportional to the input voltage, as taught by Mednik so that the supply line transients do not propagate to the power supply output.
Regarding Claim 11, Zhao teaches (Figures 3-7 and 12) the DC-DC power converter further comprising: the one or more power transistors (s1-s2); and the inductor (Lout), wherein the inductor is coupled between the input of the DC-DC converter and the one or more power transistors, or between the one or more power transistors and the output of the DC-DC converter (see fig. 3). (For Example: Par. 29-34)
Regarding Claim 12, Zhao teaches (Figures 3-7 and 12) wherein the DC-DC power converter is one of a boost converter or a buck-boost converter (see fig. 3).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhao US 2021/0211052 in view of Mednik US 2022/0200453 and further in view of Yang US 2010033136.
Regarding Claim 10, Zhao teaches (Figures 3-7 and 12) wherein the voltage control loop (with 102).
TK does not teach a transconductance amplifier having a first input terminal to receive the output voltage, a second input terminal to receive the reference voltage, and an output terminal to provide the control voltage; and a resistive-capacitive filter coupled in series between the output terminal of the transconductance amplifier and a reference voltage terminal.
Yang teaches (Figure 5) a transconductance amplifier (59) having a first input terminal to receive the output voltage (Vfb), a second input terminal to receive the reference voltage (Vref), and an output terminal to provide the control voltage (106); and a resistive-capacitive filter (60) coupled in series between the output terminal of the transconductance amplifier and a reference voltage terminal(68). (For Example: Par. 37)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of TK to include to provide an adjusted control current that is inversely proportional to the input voltage, as taught by Yang to improve transient operation of the system while providing a more stable output.
Claim(s) 20-21 and 24-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Taghizadeh-Kaschani US 2004/0012376 (Herein TK) in view of Halberstadt US 2022/0271652.
Regarding Claim 20, TK teaches (Figures 1-4) a control circuit (1, 5, 35 and 19), comprising: a voltage control loop circuit (1) having a first input terminal to receive a first voltage (4) at an output of a DC-DC power converter (Buck), a second input terminal to receive a reference voltage (2), and an output terminal (23); a first transconductance amplifier circuit (36) having a first voltage terminal coupled to the output terminal of the voltage control loop circuit (23), a second voltage terminal coupled to a first reference voltage terminal (37), and a current terminal; a second transconductance amplifier circuit (33) configurable to monitor an inductor current in the DC-DC power converter (sent to the input of 33) and having an output terminal.
TK does not teach a current control circuit having a first terminal coupled to the current terminal of the first transconductance amplifier circuit and a second terminal coupled to the output terminal of the second transconductance amplifier circuit, wherein the current control circuit is configurable to modify a control current produced by the first transconductance amplifier circuit based on a signal proportional to a second voltage at an input of the DC-DC power converter so as to produce a drive signal to control transfer of power from the input of the DC-DC power converter to the output of the DC-DC power converter.
Halberstadt teaches (Figures 1 and 3) a current control circuit (248-250 and 242) having a first terminal coupled to the current terminal of the first transconductance amplifier circuit (244, par. 50) and a second terminal coupled to the output terminal of the second transconductance amplifier circuit (246, par. 53), wherein the current control circuit is configurable to modify a control current (from 244) produced by the first transconductance amplifier circuit based on a signal proportional to a second voltage at an input of the DC-DC power converter (with 362 output signal) so as to produce a drive signal (from 104) to control transfer of power from the input of the DC-DC power converter (at Vin) to the output of the DC-DC power converter (at Vout). (For Example: Par. 46-57)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of TK to include a current control circuit having a first terminal coupled to the current terminal of the first transconductance amplifier circuit and a second terminal coupled to the output terminal of the second transconductance amplifier circuit, wherein the current control circuit is configurable to modify a control current produced by the first transconductance amplifier circuit based on a signal proportional to a second voltage at an input of the DC-DC power converter so as to produce a drive signal to control transfer of power from the input of the DC-DC power converter to the output of the DC-DC power converter, as taught by Halberstadt to improve the quality of the sensed signal and improve efficiency of the system.
Regarding Claim 21, TK teaches (Figures 1-4) the apparatus.
TK does not teach wherein the current control circuit is configurable to modify the control current produced by the first transconductance amplifier circuit based on the signal proportional to the second voltage of the DC-DC power converter so as to produce the drive signal that modifies the inductor current in response to changes in the second voltage without perturbing the first voltage.
Halberstadt teaches (Figures 1 and 3) wherein the current control circuit (242 and 248-250) is configurable to modify the control current (from 244) produced by the first transconductance amplifier circuit (244) based on the signal proportional to the second voltage of the DC-DC power converter (with 362) so as to produce the drive signal (from 104) that modifies the inductor current (114) in response to changes in the second voltage without perturbing the first voltage (the output voltage is not even sensed). (For Example: Par. 46-57)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of TK to include wherein the current control circuit is configurable to modify the control current produced by the first transconductance amplifier circuit based on the signal proportional to the second voltage of the DC-DC power converter so as to produce the drive signal that modifies the inductor current in response to changes in the second voltage without perturbing the first voltage, as taught by Halberstadt to improve the quality of the sensed signal and improve efficiency of the system.
Regarding Claim 24-25, TK teaches (Figures 1-4) the control circuit is part of the DC-DC power converter (Fig. 2) ; and wherein the DC-DC power converter is one of a boost converter (Claim 15) or a buck-boost converter.
Allowable Subject Matter
Claim 2-9 and 22-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 13-19 are allowed.
Reasons for Indicating Allowable Subject Matter
The following is an examiner’s statement of reasons for indicating Allowable Subject Matter:
Claim 2; prior art of record fails to disclose either by itself or in combination: “…wherein the reference voltage is a first reference voltage, and the current control loop comprises: a first transconductance amplifier coupled to the voltage control loop and configured to produce, at a current terminal, the control current based on the control voltage and a second reference voltage; a second transconductance amplifier configured to produce, at a sense terminal, a sense current based on the inductor current; and a current control circuit coupled to the first and second transconductance amplifiers and configured to adjust the control current to produce the adjusted control current”.
Claim 22; prior art of record fails to disclose either by itself or in combination: “…wherein the current control circuit comprises: a first transistor coupled between a voltage supply terminal and the first terminal; a first current source coupled between the voltage supply terminal and a first control terminal of the first transistor; a second transistor coupled between the voltage supply terminal and a second current source; a third current source coupled between the voltage supply terminal and a second control terminal of the second transistor, the third current source configured to produce a current proportional to the input voltage; a third transistor coupled between the first current source and a reference terminal and having a third control terminal coupled to the first terminal; and a fourth transistor coupled between the third current source and the reference terminal and having a fourth control terminal coupled to the first terminal.”
These features taken alone or in combination are neither disclosed nor suggested by the prior art of record.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838
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