DETAILED ACTION
This communication is responsive to the application, filed March 26, 2024. Claims 1-20 are pending in this application.
Examined under the first inventor to file provisions of the AIA
The present application was filed on March 26, 2024, which is on or after March 16, 2013, and thus is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Das Sharma (US 2020/0226084 A1) in view of Jeon et al. (US 11,467,909 B1).
As per claim 1: An apparatus comprising:
a port connected to a link comprising plurality of lanes to support communication between the apparatus and another device and configured to transmit a flit in a flit mode; and
Das Sharma discloses [Fig. 2A-2B; 0052-0060] the downstream and upstream ports (DSP/USP) of Figs. 2A and 2B connect to a multilane link supporting PCIe flit-based encoding. Das Sharma explicitly states for PCIe 6.0, DLLPs are part of each flit. Das Sharma further discloses [0077] the port can send an L0p DLLP encoding in a flit of the current data stream prior to a scheduled skip ordered set.
the port is configured to, after transitioning to the L0p state, transmit an ordered set (OS) through the portion of the plurality of lanes and transmit the flit through remaining lanes of the plurality of lanes.
Das Sharma discloses [Fig. 6A; 0077] the port sends SKP Ordered Sets on the lanes that will remain active and Electrical Idle Ordered Sets (EIOS) on the lanes that will go to Electrical Idle. Then the port can send data on active lanes and EIOS on electrical-idle lanes. This directly teaches transmitting ordered sets on the subset and data flits on remaining lanes.
a processor configured to control the link based on a link training and status state machine (LTSSM), wherein: the processor is configured to transition from an L0 state to an L0p state, included in the LTSSM, for a portion of the plurality of lanes based on a receiver error occurring in the portion of the plurality of lanes and based on the link reaching a specific data rate using equalization bypass, and
Das Sharma discloses [Fig. 3; 0054-0059] the PCIe LTSSM controlling link behavior, including transitions among a plurality of different states (reset, detect, polling, L0, L1, L0p, etc.) The entry to the L0p state occurs from L0 when one port intends to operate the link at a narrower width for a portion of the lanes. Some lanes are placed in electrical idle (EI) state. Das Sharma discloses transitioning from L0 to L0p state for a portion of lanes, but fails to explicitly disclose transition based on a receiver error occurring in the portion of the plurality of lanes and based on equalization bypass. Jeon discloses a similar system, which further teaches [Fig. 6; col. 8, lines 22-38] the recovery state may be used to reconfigure a link bandwidth. In the recovery state, an equalization operation of the link may be performed. The recovery state may be entered when an error occurs in the L0 state (receiver error in L0 state). The transition is triggered by error and the equalization is performed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Das Sharma with that of Jeon. One would have been motivated to transitioning based on a receiver error occurring using equalization bypass because it allows to improve the quality of signals being transmitted and received [Jeon; col. 9, lines 7-15].
As per claim 2: The apparatus of claim 1, wherein the equalization bypass skips equalization of a plurality of data rates lower than the specific data rate.
Jeon discloses [col. 9, lines 5-20] equalization bypass operation may be skipped at a specific data rate, and the upstream and the downstream port may advertise the specific data rate at which the equalization operation is skipped.
As per claim 15: A method comprising:
transmitting an ordered set (OS) through the portion of the plurality of lanes and transmitting a flit through remaining lanes of the plurality of lanes.
Das Sharma discloses [Fig. 2A-2B; 0052-0060] the downstream and upstream ports (DSP/USP) of Figs. 2A and 2B connect to a multilane link supporting PCIe flit-based encoding. Das Sharma explicitly states for PCIe 6.0, DLLPs are part of each flit. Das Sharma further discloses [0077] the port can send an L0p DLLP encoding in a flit of the current data stream prior to a scheduled skip ordered set. Das Sharma further discloses [Fig. 6A; 0077] the port sends SKP Ordered Sets on the lanes that will remain active and Electrical Idle Ordered Sets (EIOS) on the lanes that will go to Electrical Idle. Then the port can send data on active lanes and EIOS on electrical-idle lanes. This directly teaches transmitting ordered sets on the subset and data flits on remaining lanes.
transitioning from an L0 state to an L0p state, included in a link training and status state machine (LTSSM), for a portion of a plurality of lanes included in a link based on a receiver error occurring in the portion of the plurality of lanes and based on the link reaching a specific data rate using equalization bypass; and
Das Sharma discloses [Fig. 3; 0054-0059] the PCIe LTSSM controlling link behavior, including transitions among a plurality of different states (reset, detect, polling, L0, L1, L0p, etc.) The entry to the L0p state occurs from L0 when one port intends to operate the link at a narrower width for a portion of the lanes. Some lanes are placed in electrical idle (EI) state. Das Sharma discloses transitioning from L0 to L0p state for a portion of lanes, but fails to explicitly disclose transition based on a receiver error occurring in the portion of the plurality of lanes and based on equalization bypass. Jeon discloses a similar system, which further teaches [Fig. 6; col. 8, lines 22-38] the recovery state may be used to reconfigure a link bandwidth. In the recovery state, an equalization operation of the link may be performed. The recovery state may be entered when an error occurs in the L0 state (receiver error in L0 state). The transition is triggered by error and the equalization is performed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Das Sharma with that of Jeon. One would have been motivated to transitioning based on a receiver error occurring using equalization bypass because it allows to improve the quality of signals being transmitted and received [Jeon; col. 9, lines 7-15].
As per claim 20: A storage device comprising:
a nonvolatile memory;
Das Sharma discloses [0034] memory, such as non-volatile memory, can be dedicated to processor or shared with other devices in a system.
a port connected to a link comprising a plurality of lanes to support communication between the storage device and another device and configured to transmit a flit in a flit mode; and
Das Sharma discloses [Fig. 2A-2B; 0052-0060] the downstream and upstream ports (DSP/USP) of Figs. 2A and 2B connect to a multilane link supporting PCIe flit-based encoding. Das Sharma explicitly states for PCIe 6.0, DLLPs are part of each flit. Das Sharma further discloses [0077] the port can send an L0p DLLP encoding in a flit of the current data stream prior to a scheduled skip ordered set.
and the port is configured to, after transitioning to the L0p state, transmit an ordered set (OS) through the portion of the plurality of lanes and transmit the flit through remaining lanes of the plurality of lanes.
Das Sharma discloses [Fig. 6A; 0077] the port sends SKP Ordered Sets on the lanes that will remain active and Electrical Idle Ordered Sets (EIOS) on the lanes that will go to Electrical Idle. Then the port can send data on active lanes and EIOS on electrical-idle lanes. This directly teaches transmitting ordered sets on the subset and data flits on remaining lanes.
a controller configured to control the link based on a link training and status state machine (LTSSM), wherein:
the controller is configured to transition the storage device from an L0 state to an L0p state, included in the LTSSM, for a portion of the plurality of lanes based on a receiver error occurring in the plurality of lanes and based on the link reaching a specific data rate using equalization bypass,
Das Sharma discloses [Fig. 3; 0054-0059] the PCIe LTSSM controlling link behavior, including transitions among a plurality of different states (reset, detect, polling, L0, L1, L0p, etc.) The entry to the L0p state occurs from L0 when one port intends to operate the link at a narrower width for a portion of the lanes. Some lanes are placed in electrical idle (EI) state. Das Sharma discloses transitioning from L0 to L0p state for a portion of lanes, but fails to explicitly disclose transition based on a receiver error occurring in the portion of the plurality of lanes and based on equalization bypass. Jeon discloses a similar system, which further teaches [Fig. 6; col. 8, lines 22-38] the recovery state may be used to reconfigure a link bandwidth. In the recovery state, an equalization operation of the link may be performed. The recovery state may be entered when an error occurs in the L0 state (receiver error in L0 state). The transition is triggered by error and the equalization is performed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Das Sharma with that of Jeon. One would have been motivated to transitioning based on a receiver error occurring using equalization bypass because it allows to improve the quality of signals being transmitted and received [Jeon; col. 9, lines 7-15].
Allowable Subject Matter
Claims 3-14 and 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. More specifically, claim 3 which depends on independent claim 1 and claim 16 which depends on independent claim 15 recite the L0p state comprises a first, second, third, fourth, and fifth L0p sub-states. The sub-states described in the specification and further dependent claims make it clear that they are sub-states related to L0p.Entry, L0p.RcvrLock, L0p.RcvrCfg, L0p.Idle, and L0p.Equalization. The cited prior art references teach recovery sub-states during equalization and recovery. Therefore, the cited prior art references sub-stages occur during link training/error recovery phases. However, none of the cited prior art references specifically disclose or suggest entering the plurality of sub-states during an L0p state (power saving state in PCIe 6.0). Therefore, claims 3 and 16 are objected to be allowable. Claims 4-14 depend from claim 3 and are therefore objected to be allowable based on their dependencies. Claims 17-19 depend from claim 16 and are therefore objected to be allowable based on their dependencies.
Conclusion
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
· US 2014/0281753 A1 – Wagh discloses handling a timeout error in LTSSM and using a state machine to train serial links and/or form a link from multiple lanes. All modules of a port undergoing link state training placed into an intermediate state prior to entry into the lowest power state.
· US 2024/0111700 A1 – Srivastava discloses providing an interface with a multiple lane data link, the data link having a first set of lanes in an active state and a second set of lanes in an idle state. The link can operate in an L0p sub-state, which is not an inactive or idle state.
· US 2022/0004453 A1 – Wong discloses using idle flow control (flits) to maintain link continuity. The data link layer is configured to remove idle flits of the first size received from the physical layer and to report CRC errors.
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/JIGAR P PATEL/Primary Examiner, Art Unit 2114