DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 11th, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
This is in response to applicant’s amendment/response filed on 03/03/2026 which have been entered and made of record.
Applicant’s arguments with respect to claim(s) 1-2, 4, 7-10, 12, 15-16, and 18-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4, 7-10, 12, 15-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hutchins et al. U.S. Patent 6657635 B1 (hereinafter Hutchins) in view of NPL “Rendering Elimination: Early Discard of Redundant Tiles in the Graphics Pipeline” by Marti Anglada, Enrique de Lucas, Joan-Manuel Parcerisa, Juan L. Aragon, Pedro Marcuello, and Antonio Gonzalez (hereinafter Anglada) in further view of Ray et al. U.S. Patent 10802967 B1 (hereinafter Ray).
Regarding claim 1, Hutchins teaches a method comprising:
rendering a scene (Scene, Images, Geometry) comprising one or more graphics objects (Col.1 Lines 32-41) in a display space (Col.2 Lines 37-57) that is divided into a plurality of tiles (Col.2 Lines 58-67 and Col.3 1-13), comprising:
determining that contents of at least two tiles of the plurality of (Col. 6 Lines 42-59 and Col. 5 Lines 11-31); Tiles states are tracked throughout the rendering process and multiple tiles can be chosen to be flushed. Thus, tiles can be tracked and determined to no longer be needed and flushed from memory.
and (Another Tile in First Render Pass) of the at least two tiles to match a first write back memory address (Binning Memory) associated with a first tile (Tile in First Render Pass) of the at least two tiles. (Col.6 Lines 17-41) During the first partial render pass a tile or multiple tiles are stored in the binning memory. Each tile can be stored in the same binning memory. Thus, multiple tiles can have their memory address changed to be written to the same memory address.
However, Hutchins fails to explicitly teach:
determining tiles are no longer used;
changing write back memory addresses.
Hutchins and Anglada are analogous to the claimed invention because both of them are in the same field of rendering tiles in the graphics pipeline.
Anglada teaches:
determining that contents of at least two tiles (Redundant Tiles) of the plurality of tiles are no longer used (Skip Rending Process) after a current render pass (Rendering Elimination Bypass or Transaction Elimination Bypass, Section: 1. Introduction, Page 624 Para. 4-5 Fig. 3). Anglada teaches several methods used to detect redundant tiles during tile-based rendering. The Rendering Elimination Bypass skips the entire Raster Pipeline of said redundant tile and Transaction Elimination Bypass skips a portion of the Raster Pipeline (Section: 1. Introduction, Pages 623-624). When a tile is determined to be redundant using Rendering Elimination Bypass the tile is no longer used as previous data in the buffers are reused (Section: 1. Introduction, Page 624 Para. 4-5).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hutchins Tile Based Rendering to incorporate Anglada’s Rendering Elimination Bypass. Since doing so would provide the benefit of reducing execution time and increasing computation speeds (Anglada et al. Section: V. Experimental Results Page 631).
However, Hutchins and Anglada fails to explicitly teach:
and changing a second write back memory address associated with a second tile of the at least two tiles to match a first write back memory address associated with a first tile of the at least two tiles.
Hutchins, Anglada, and Ray are analogous to the claimed invention because all of them are in the same field of rendering tiles in the graphics pipeline.
Ray teaches:
and changing a second write back memory address (Byte Address A+1) associated with a second tile (Tile-1) of the at least two tiles to match a first write back memory address (Byte Address A) associated with a first tile (Tile-0) of the at least two tiles. Tile-1 writes to address A overwriting the data (Col. 35 Lines 29-53).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hutchins Tile Based Rendering altered by Anglada’s Rendering Elimination Bypass to incorporate Ray’s Changing of Write Back Memory Addresses. Since doing so would provide the benefit of honoring per-thread read-write ordering in Open CL memory model where different threads on different tiles write to different bytes. (Col. 35 Lines 29-53)
Regarding claim 2, Hutchins teaches the method of claim 1, further comprising: subsequent to performing the current render pass (Second Render Pass), (Tiles from First Render Pass) with data of the second tile (Tiles from Second Render Pass) at the first write back memory address (Binning Memory). (Col.6 Lines 17-42) Tiles in the second pass can overwrite the tiles in the binning memory from the first partial render pass.
However, Hutchins and Anglada fail to explicitly teach:
overwriting data of the first tile with data of the second tile at the first write back memory address.
Ray teaches:
overwriting data of the first tile (Tile-0) with data of the second tile (Tile-1) at the first write back memory address (Byte Address A). (Col. 35 Lines 29-53)
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hutchins Tile Based Rendering altered by Anglada’s Rendering Elimination Bypass to incorporate Ray’s Overwriting of Data. Since doing so would provide the benefit of honoring per-thread read-write ordering in Open CL memory model where different threads on different tiles write to different bytes. (Col. 35 Lines 29-53)
Regarding claim 4, Hutchins teaches the method of claim 1, wherein determining that the contents of the at least (CPU/Processor, Col. 2 Lines 58-67 and Col. 3 Lines 1-27) that the contents of the at least two tiles are no longer used. (Col. 6 Lines 42-59 and Col. 5 Lines 11-31) A CPU/Processor is used to perform the binning operations. Thus, tile states are tracked by the CPU/Processor.
However, Hutchins fails to explicitly teach:
determining that the contents of the at least two tiles are no longer used
Anglada teaches:
wherein determining that the contents of the at least two tiles (Redundant Tiles) are no longer used (Skip Rendering Process) comprises receiving an indication from a driver (Signature Buffer and Signature Unit, Fig. 5) that the contents of the at least two tiles are no longer used(Redundant Tiles). Anglada compares signatures of tiles, those signatures that match the previous frame skip the raster pipeline execution (Section: II. Rendering Elimination, Pages 625-626).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hutchins Tile Based Rendering to incorporate Anglada’s Rendering Elimination Bypass. Since doing so would provide the benefit of reducing execution time and increasing computation speeds (Anglada et al. Section: V. Experimental Results Page 631).
Regarding claim 7, Hutchins teaches the method of claim 1, wherein at least two of the plurality of tiles have different sizes. (Col. 6 Lines 17-42) Tiles are processed based on tile size. Thus, multiple tiles have different sizes.
Regarding claim 8, Hutchins teaches the method of claim 1, further comprising: dividing the display space into the plurality of tiles (Col.2 Lines 58-67 and Col.3 1-13), comprising determining a tile size based on a cache (Binning Memory) size of a cache that is to store at least some of the plurality of tiles after they are rendered. (Col. 5 Lines 32-44) Every tile needs to hold a bare minimum amount of memory in relation to the size of the binning memory. Thus, the tile size is related to the size of the binning memory.
Regarding claim 9, Hutchins teaches the method of claim 8, wherein the cache (Binning Memory) comprises a memory location addressed by the first write back memory address (Binning Memory Address). (Col. 6 Lines 17-42)
Regarding claim 10, Hutchins teaches a processor and graphics core (Graphics System/Processor, Col. 2 Lines 37-57) for performing the method of claim 1, therefore it is rejected under the same rationale as claim 1.
Regarding claim 12, has similar limitations as of claim 4, therefore it is rejected under the same rationale as claim 4.
Regarding claim 15, has similar limitations as of claim 7, therefore it is rejected under the same rationale as claim 7.
Regarding claim 16, Hutchins teaches a processing system, comprising:
a bus; (Col. 2 Lines 37-57)
a first processing circuit configured to issue a plurality of commands via the bus; (Col. 2 Lines 37-57, Fig.1)
and a second processing circuit configured to receive the plurality of commands from the first processing circuit (Col. 2 Lines 37-57, Fig. 1), and comprising:
a cache; (Binning Memory, Col. 5 Lines 32-44)
a graphics core (Graphics System/Processor,) associated with a plurality of tiles of a display space (Col. 2 Lines 37-57) and configured to:
determine that contents of at least two tiles of the plurality of (Col. 6 Lines 42-59 and Col. 5 Lines 11-31); Tiles states are tracked throughout the rendering process and multiple tiles can be chosen to be flushed. Thus, tiles can be tracked and determined to no longer be needed and flushed from memory.
and (Binning Memory) associated with a second tile (Another Tile in First Render Pass) of the at least two tiles to match a first write back memory address of the cache (Binning Memory) associated with a first tile (Tile in First Render Pass) of the at least two tiles. (Col.6 Lines 17-41) During the first partial render pass a tile or multiple tiles are stored in the binning memory. Each tile can be stored in the same binning memory. Thus, multiple tiles can have their memory address changed to be written to the same memory address.
However, Hutchins fails to explicitly teach:
determining tiles are no longer used;
changing write back memory addresses.
Hutchins and Anglada are analogous to the claimed invention because both of them are in the same field of rendering tiles in the graphics pipeline.
Anglada teaches:
determining that contents of at least two tiles (Redundant Tiles) of the plurality of tiles are no longer used (Skip Rending Process) after a current render pass (Rendering Elimination Bypass or Transaction Elimination Bypass, Section: 1. Introduction, Page 624 Para. 4-5 Fig. 3). Anglada teaches several methods used to detect redundant tiles during tile-based rendering. The Rendering Elimination Bypass skips the entire Raster Pipeline of said redundant tile and Transaction Elimination Bypass skips a portion of the Raster Pipeline (Section: 1. Introduction, Pages 623-624). When a tile is determined to be redundant using Rendering Elimination Bypass the tile is no longer used as previous data in the buffers are reused (Section: 1. Introduction, Page 624 Para. 4-5).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hutchins Tile Based Rendering to incorporate Anglada’s Rendering Elimination Bypass. Since doing so would provide the benefit of reducing execution time and increasing computation speeds (Anglada et al. Section: V. Experimental Results Page 631).
However, Hutchins and Anglada fail to explicitly teach:
and changing a second write back memory address associated with a second tile of the at least two tiles to match a first write back memory address associated with a first tile of the at least two tiles.
Hutchins, Anglada, and Ray are analogous to the claimed invention because all of them are in the same field of rendering tiles in the graphics pipeline.
Ray teaches:
and changing a second write back memory address (Byte Address A+1) associated with a second tile (Tile-1) of the at least two tiles to match a first write back memory address (Byte Address A) associated with a first tile (Tile-0) of the at least two tiles. Tile-1 writes to address A overwriting the data (Col. 35 Lines 29-53).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hutchins Tile Based Rendering altered by Anglada’s Rendering Elimination Bypass to incorporate Ray’s Changing of Write Back Memory Addresses. Since doing so would provide the benefit of honoring per-thread read-write ordering in Open CL memory model where different threads on different tiles write to different bytes. (Col. 35 Lines 29-53)
Regarding claim 18, has similar limitations as of claims 4 and 12, therefore it is rejected under the same rationale as claims 4 and 12.
Regarding claim 19, Hutchins teaches the processing system of claim 16, further comprising: a memory (Graphics Memory, Col. 2 Lines 58-67 and Col.3 1-13) configured to store data, wherein the second processing circuit is configured to copy data from the cache (Binning Memory) to the memory as part of removing that data from the cache (Binning Memory). (Col. 3 Lines 43-65) Tile data can be flushed from memory to free up space, thus removing it from memory.
However, Hutchins and Anglada fails to explicitly teach the second processing circuit is configured to copy data from the cache to the memory as part of removing that data from the cache.
Ray teaches the second processing circuit (Tiled Graphics Processing Configuration, Col. 35 Lines 22-30) is configured to copy data from the cache to the memory (Writing Cache Line to Memory) as part of removing (Evicting Data From Cache) that data from the cache. Ray teaches writing cache lines to memory and evicting them (Col. 35 Lines 29-53). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hutchins Tile Based Rendering altered by Anglada’s Rendering Elimination Bypass to incorporate Ray’s Changing of Write Back Memory Addresses. Since doing so would provide the benefit of honoring per-thread read-write ordering in Open CL memory model where different threads on different tiles write to different bytes. (Col. 35 Lines 29-53)
Regarding claim 20, Hutchins teaches the processing system of claim 19, wherein changing the second write back memory address (Binning Memory) causes the second processing circuit (Col. 2 Lines 37-57, Fig. 1) to write either write back data associated with the first tile(Tiles in First Pass) or write back data associated with the second tile (Tiles in Second Render Pass) , (Col.6 Lines 17-42) Tiles in the second pass can overwrite the tiles in the binning memory from the first partial render pass. Tiles can be flushed and stored one by one or multiple at a time. (Col. 6 Lines 42-59)
However, Hutchins and Anglada fail to explicitly teach:
but not both, from the cache to the memory.
Ray teaches the processing system of claim 19, wherein changing the second write back memory address (Byte Address A+1) causes the second processing circuit (Tiled Graphics Processing Configuration, Col. 35 Lines 22-30) to write either write back data associated with the first tile (Tile-0) or write back data associated with the second tile (Tile-1), (Col. 35 Lines 29-53) but not both, from the cache to the memory. Each tile can be independently read/modify/write to cache lines and can overwrite other data, Col. 36 Lines 62-67 to Col. 37 Lines 1-2. Thus one of the Tiles can write back and not the other. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hutchins Tile Based Rendering altered by Anglada’s Rendering Elimination Bypass to incorporate Ray’s Changing of Write Back Memory Addresses. Since doing so would provide the benefit of honoring per-thread read-write ordering in Open CL memory model where different threads on different tiles write to different bytes. (Col. 35 Lines 29-53)
Claim(s) 3, 5-6, 11, 13-14, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hutchins et al. U.S. Patent 6657635 B (hereinafter Hutchins) in view of NPL “Rendering Elimination: Early Discard of Redundant Tiles in the Graphics Pipeline” by Marti Anglada, Enrique de Lucas, Joan-Manuel Parcerisa, Juan L. Aragon, Pedro Marcuello, and Antonio Gonzalez (hereinafter Anglada) in further view of Ray et al. U.S. Patent 10802967 B1 (hereinafter Ray) in further view of Bolz et al. U.S. Patent Application Publication 20160077896 A1 (hereinafter Bolz).
Regarding claim 3, Hutchins teaches their graphics system can implement software and an interface controller(Col. 3 Lines 14-27).
However, Hutchins fails to explicitly teach the method of claim 1, wherein determining that the contents of the at least two tiles are no longer used comprises receiving an indication from an application programming interface (API) that the at least two tiles are no longer used.
Anglada teaches the method of claim 1, wherein determining that the contents of the at least two tiles (Redundant Tiles) are no longer used(Skip Rending Process) comprises receiving an indication from an (Signature Buffer and Signature Unit, Fig. 5) that the at least two tiles(Redundant Tiles) are no longer used (Skip Rending Process). (Rendering Elimination Bypass or Transaction Elimination Bypass, Section: 1. Introduction, Page 624 Para. 4-5 Fig. 3). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hutchins Tile Based Rendering to incorporate Anglada’s Rendering Elimination Bypass. Since doing so would provide the benefit of reducing execution time and increasing computation speeds (Anglada et al. Section: V. Experimental Results Page 631).
However, Hutchins, Anglada and Ray fail to explicitly teach receiving an indication from an application programming interface (API) that the at least two tiles are no longer used.
Hutchins, Anglada, Ray, and Bolz are analogous to the claimed invention because all of them are in the same field of Tile based rendering.
Bolz teaches the method of claim 1, wherein determining that the contents of the at least two tiles are no longer used comprises receiving an indication from an application programming interface (API) that the at least two tiles are no longer used. (Para. 0003, 0022-0023, and 0026) Bolz API tracks the states of the tiles and the dependencies. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hutchins Tile Based Rendering altered by Anglada’s Rendering Elimination Bypass and Ray’s Changing of Write Back Memory Addresses to incorporate Bolz’s API and Dependency tracking. Since doing so would provide the benefit of utilizing an API. As API’s are a common aspect of computing systems and increase the efficiency of communication within the system as it can access hardware resources. (Bolz, Para. 0002) As well as drivers are used with APIs to support processing of commands in a graphics processor (Ray et al. Col. 26 Lines 44-64)
Regarding claim 5, Hutchins, Anglada, and Ray fail to teach the method of claim 4, wherein receiving the indication from the driver comprises the driver analyzing a data dependency graph corresponding to the display space.
However, Bolz teaches the method of claim 4, wherein receiving the indication from the driver comprises the driver analyzing a data dependency graph (Dependencies/True Dependencies, Para. 0019-0020, 0022-0023, and 0065) corresponding to the display space. (Para. 0003, Para. 0127) Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hutchins Tile Based Rendering altered by Anglada’s Rendering Elimination Bypass and Ray’s Changing of Write Back Memory Addresses to incorporate Bolz’s Dependency tracking. Since doing so would provide the benefit of advantageously specify dependencies for memory tiling which are simpler and more efficient for driver/applications to implement. (Bolz, Para. 0127)
Regarding claim 6, Hutchins teaches their graphics system can implement software and an interface controller(Col. 3 Lines 14-27).
However, Hutchins and Anglada fail to explicitly teach the method of claim 4, wherein receiving the indication from the driver comprises the driver receiving the indication via an application programming interface (API) from an application that generates data of the scene.
Ray teaches the method of claim 4, wherein receiving the indication from the driver comprises the driver receiving the indication via an application programming interface (API) (Col. 26 Lines 44-63) from an application Ray teaches utilizing a graphics driver 1026 that receives OpenGL API instructions/commands (Col. 29 Lines 58-67 to Col. 30 Lines 1-20) to process them. The various APIs stated in Ray involve pixels, colors, shaders (Col. 20 Lines 8-30 and Col. 30 Lines 9-20). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hutchins Tile Based Rendering altered by Anglada’s Rendering Elimination Bypass to incorporate Ray’s Graphics Pipeline that Supports API.
However, Ray fails to explicitly state from an application that generates data of the scene.
Bolz teaches the method of claim 4, wherein receiving the indication from the driver comprises the driver receiving the indication (0017-0018) via an application programming interface (API) from an application that generates data (Image Data) of the scene. (Para. 0003, 0022-0023, and 0026) Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hutchins Tile Based Rendering altered by Anglada’s Rendering Elimination Bypass and Ray’s Graphics Pipeline that Supports API to incorporate Bolz API and Dependency tracking. Since doing so would provide the benefit of utilizing an API. As API’s are a common aspect of computing systems and increase the efficiency of communication within the system as it can access hardware resources. (Bolz, Para. 0002)
Regarding claim 11, has similar limitations as of claim 3, therefore it is rejected under the same rationale as claim 3.
Regarding claim 13, has similar limitations as of claim 5, therefore it is rejected under the same rationale as claim 5.
Regarding claim 14, has similar limitations as of claim 6, therefore it is rejected under the same rationale as claim 6.
Regarding claim 17, has similar limitations as of claims 3 and 11, therefore it is rejected under the same rationale as claims 3 and 11.
Conclusion
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/BRIANNA RENAE COCHRAN/Examiner, Art Unit 2615
/ALICIA M HARRINGTON/Supervisory Patent Examiner, Art Unit 2615
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