DETAILED ACTION
This action is in response to an amendment filed on December 22, 2025 for the application of Bala et al., for a “Shared memory freedom from interference system for securing critical and non-critical data” filed on March 26, 2024. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The information disclosure statement (IDS) submitted on has been considered.
Claims 1-16 and 17-21 are pending in the application.
Claim 17 has been cancelled.
Claim 21 has been added.
Claims 12, 16, and 18-20 have been amended.
Claims 1, 4, 7-11, and 21 are rejected under 35 USC § 103.
Claims 16 and 18-20 are allowed.
Claims 2-3, 5-6, and 12-15 are objected to while containing allowable matter.
Specification
In view of the applicant’s amendments to the title of the invention, the previous objections have been withdrawn.
Claim Rejections - 35 USC § 112
In view of the applicant’s amendments/arguments, the previous rejection of claim has been withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 9, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Usami et al. (U.S. PGPUB 20150019154) in view of Eckert (U.S. PGPUB 20190065243).
As per claim 1, Usami discloses a system comprising:
a memory circuit (fig. 1) comprising:
a first memory portion configured to store critical data; and a second memory portion configured to store non-critical data ([0023], “safety-critical data important to safety and safety-uncritical data having little effect on safety”); and
an arbiter circuit ([0079], “memory control unit 80 to perform access control”) configured to transmit first memory requests and corresponding data between a first processing circuit configured to perform critical processes and the memory circuit ([0079], “The first processing 41 supplies the memory control unit 80 with the safety-critical data and the writing request for storing the safety-critical data received from the second processing 42. The memory control unit 80 stores the safety-critical data received from the first processing 41 into the memory 20 in accordance with the writing request for storing the safety-critical data.”), transmit second memory requests and corresponding data between a second processing circuit configured to perform non-critical processes and the memory circuit ([0079], “The second processing 42 performs a second processing with reference to safety-uncritical data which is less critical than the safety-critical data.”), and prevent unauthorized memory ([0077], “it is possible to clearly divide the writing and read-out authorizations, so that only the first processing 41 can perform read-out and writing of the data D1 important to safety, based on requests from the second processing 42, and so that only the second processing 42 can perform read-out and writing of the data D2 having little effect on safety”) requests from the first and second processing circuits to the memory circuit ([0079], “The first processing 41 and the second processing 42 are prohibited from storing the safety-critical data into the memory 20. In this manner, by providing the memory control unit 80 to perform access control, it is not only possible to reduce the processing burden related to access control by the CPU 40, but also possible to achieve more secure access control”).
Usami fails to explicitly disclose the second memory portion is independent from the first memory portion.
Eckert of analogous art teaches:
wherein the second memory portion is independent from the first memory portion ([0024], “In some embodiments, memory 160 includes a plurality of memory modules. Each of the memory modules includes one or more memory devices (e.g., memory chips) mounted thereon. In some embodiments, memory 160 includes one or more memory devices mounted on a motherboard or other carrier upon which SoC 105 is also mounted. In some embodiments, at least a portion of memory 160 is implemented on the die of SoC 105 itself”).
All of the claimed elements were known in Usami and Eckert and could have been combined by known methods with no change in their respective functions. It therefore would have been obvious to a person of ordinary skill in the art before the time of effective filing language to combine their memory access control methods. One would be motivated to make this combination since Eckert’s memory is a mere example of Usami’s memory.
As per claim 9, Eckert discloses the memory circuit is a static random-access memory ([0024], “SRAM”) or a cache ([0025]).
As per claim 21, Eckert discloses the first memory portion is one memory bank of a memory and the second memory portion is another memory bank of the memory ([0036], “Each chip 260A-N of ranks 255A-N includes any number of banks, with each bank including any number of storage locations.”); or the first memory portion is one cache of a cache hierarchy and the second memory portion is another cache of the cache hierarchy ([0025]).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Usami et al. (U.S. PGPUB 20150019154) in view of Eckert (U.S. PGPUB 20190065243) and in further view of Enapakurthi et al. (U.S. PGPUB 20250091436).
As per claim 7, Usami fails to explicitly disclose wherein the arbiter circuit is integrated into an automobile.
Enapakurthi of analogous art teaches:
wherein the arbiter circuit is integrated into an automobile and wherein the critical processes ([0073], “critical safety information”) include making a sound when a door of the automobile is open, displaying a speedometer, connecting audio of an emergency telephone call to at least one speaker of the automobile, enabling a turn signal of the automobile, enabling headlights of the automobile, making a sound to alert pedestrians to a location of the automobile, or any combination thereof ([0073]).
All of the claimed elements were known in Usami and Enapakurthi and could have been combined by known methods with no change in their respective functions. It therefore would have been obvious to a person of ordinary skill in the art before the time of effective filing language to combine their methods. One would be motivated to make this combination since Enapakurthi’s safety critical information is a mere example of Usami’s safety critical data.
As per claim 8, Enapakurthi discloses the arbiter circuit is integrated into an automobile and wherein the non-critical processes ([0074], “noncritical vehicle information”) include connecting radio audio to at least one speaker of the automobile, connecting audio of a non-emergency telephone call to at least one speaker of the automobile, activating a display of an entertainment system of the automobile, or any combination thereof ([0074]).
Claims 4 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Usami et al. (U.S. PGPUB 20150019154) in view of Eckert (U.S. PGPUB 20190065243) and in further view of Strongin et al. (U.S. Patent No. 7426644).
As per claim 4, Usami in view of Eckert fails to explicitly disclose raising an exception.
Strongin of analogous art teaches preventing unauthorized memory requests (col. 2, lines 49-51, “The contents of the U/S and R/W bits are used by the operating system to protect corresponding page frames (i.e., memory pages) from unauthorized access”) comprises raising an exception in response to the first processing circuit attempting to write critical data to the second memory portion (col. 12, TABLE 1, “if selected memory page is a secure page (SP = 1), a SEM Security Exception is raised”) or raising an exception in response to the second processing circuit attempting to write non-critical data to the first memory portion.
All of the claimed elements were known in Usami and Strongin and could have been combined by known methods with no change in their respective functions. It therefore would have been obvious to a person of ordinary skill in the art before the time of effective filing language to combine their memory access control methods. One would be motivated to make this combination since Strongin’s exception is a mere example of Usami’s communication error ([0042] and [0051]).
As per claim 10, Usami discloses a method, comprising:
receiving, at an arbiter circuit from a processing circuit ([0079], “memory control unit 80 to perform access control”), a first memory request that addresses a first memory portion configured to store critical data ([0079], “The first processing 41 supplies the memory control unit 80 with the safety-critical data and the writing request for storing the safety-critical data received from the second processing 42.”);
issuing the first memory request in response to determining that the processing circuit is performing a critical process ([0079], “The first processing 41 supplies the memory control unit 80 with the safety-critical data and the writing request for storing the safety-critical data received from the second processing 42. The memory control unit 80 stores the safety-critical data received from the first processing 41 into the memory 20 in accordance with the writing request for storing the safety-critical data.”);
receiving, from the processing circuit, a second memory request that addresses a second memory portion configured to store non-critical data ([0079], “The second processing 42 performs a second processing with reference to safety-uncritical data which is less critical than the safety-critical data.”); and
Usami fails to explicitly disclose the second memory portion is independent from the first memory portion.
Eckert of analogous art teaches:
wherein the second memory portion is independent from the first memory portion ([0024], “In some embodiments, memory 160 includes a plurality of memory modules. Each of the memory modules includes one or more memory devices (e.g., memory chips) mounted thereon. In some embodiments, memory 160 includes one or more memory devices mounted on a motherboard or other carrier upon which SoC 105 is also mounted. In some embodiments, at least a portion of memory 160 is implemented on the die of SoC 105 itself”).
All of the claimed elements were known in Usami and Eckert and could have been combined by known methods with no change in their respective functions. It therefore would have been obvious to a person of ordinary skill in the art before the time of effective filing language to combine their memory access control methods. One would be motivated to make this combination since Eckert’s memory is a mere example of Usami’s memory.
Usami in view of Eckert fails to explicitly disclose raising an exception.
Strongin of analogous art teaches raising an exception in response to the second memory request and in response to determining that the processing circuit is performing the critical process (col. 12, TABLE 1, “if selected memory page is a secure page (SP = 1), a SEM Security Exception is raised”).
All of the claimed elements were known in Usami and Strongin and could have been combined by known methods with no change in their respective functions. It therefore would have been obvious to a person of ordinary skill in the art before the time of effective filing language to combine their memory access control methods. One would be motivated to make this combination since Strongin’s exception is a mere example of Usami’s communication error ([0042] and [0051]).
As per claim 11, Eckert discloses the first memory portion corresponds to a first memory circuit and the second memory portion corresponds to a second memory circuit ([0023]-[0024]).
Allowable Subject Matter
Claims 2-3, 5-6, 12-15 are objected to as being dependent upon a rejected base claim. Claims 2-3, 5-6, 12-15 would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments see pages 9-10, filed on December 22, 2025 with respect to the rejection(s) of claim(s) 1 and 10 under 35 USC § 102/103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made over Claims 4 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Usami et al. (U.S. PGPUB 20150019154) in view of Eckert (U.S. PGPUB 20190065243) and in further view of Strongin et al. (U.S. Patent No. 7426644). Refer to the corresponding section of the claim analysis for details.
In view of the applicant’s amendments to claim 16, the previous rejections have been withdrawn. Claims 16 and 18-20 are allowed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See included PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Elmira Mehrmanesh whose telephone number is (571)272-5531. The examiner can normally be reached on M-F from 10-6.
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/Elmira Mehrmanesh/
Primary Examiner, Art Unit 2113
Prosecution Insights