DETAILED ACTION
Claims 1-16 are presented for examination.
The present application is being examined under the AIA (America Invents Act) First Inventor to File.
This Office Action is Non-Final.
Claims 1 and 11 are independent claims. Claims 2-10, 12-16 are dependent claims.
This action is responsive to the following communication: corresponding claims filed on 03-26-2024.
Foreign Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file. It is also noted, that applicant has filed a certified copy on 05-06-2024 as required by 35 U.S.C. 119(b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2025/0060801 (hereinafter, Ma) in view of U.S. Publication No. 2012/0124406 (hereinafter Lu).
As per claims 1, 16, Ma discloses a power management method adapted for a computer system that includes a central processing unit (CPU), a control unit, a basic input/output system (BIOS), and multiple power supply units (PSUs) that include a first PSU, said power management method comprising steps of:
A) when the first PSU operates in a predefined abnormal condition, (“PSU has faults”; ¶ [004] )the first PSU changing an alert signal, (triggering an “alert signal”; ¶[004] which is sent by the first PSU to the control unit, (Complex Programmable Logic Device (CPLD) ; ¶ [004]) from a non-alert state to an alert state; (¶ [004] discloses a process of triggering an alert signal, in which to a PHOSITA would recognize that the state of the alert signal prior to be generated would have to non-alert state)
B) when detecting the change of the alert signal from the non-alert state to the alert state, the control unit changing a throttling signal, which is sent by the control unit to the CPU, from a non-throttling state to a throttling state, so that the CPU operates under restriction of a predefined lowest power consumption limit; (¶ [004] states “triggering Central Processing Unit (CPU) throttling by a Power Supply Unit (PSU) Alert signal. When the PSU has faults such as over-temperature or over-current alerts, the PSU Alert signal is pulled down. Once detecting that the PSU Alert signal is pulled down, a Complex Programmable Logic Device (CPLD) triggers CPU throttling, and the CPU in the server will then operate at a lower frequency, thereby significantly reducing system power consumption.” )
C) when detecting the change of the alert signal from the non-alert state to the alert state, (triggering an alert signal; ¶ [004])
Ma does not distinctly disclose the following:
the control unit computing and sending, based on one of a maximum output power value of the first PSU and a total maximum output power value of the PSU(s) other than the first PSU, an updated power consumption limit that is greater than the predefined lowest power consumption limit to the BIOS;
D) when receiving the updated power consumption limit, the BIOS outputting a first system management interrupt to the CPU, and writing the updated power consumption limit into a model-specific register of the CPU; and
E) after step D), the BIOS notifying the control unit to change the throttling signal from the throttling state to the non-throttling state, so that the CPU operates under restriction of the updated power consumption limit according to the model-specific register.
However, Lu discloses the following:
the control unit computing and sending, based on one of a maximum output power value of the first PSU and a total maximum output power value of the PSU(s) other than the first PSU, an updated power consumption limit that is greater than the predefined lowest power consumption limit to the BIOS; (¶ [0019] states the health states of the power supplies are detected, and the output powers provided by the power supplies are received to acquire the total maximum output power of the power supplies capable of providing power” , ¶ [0018] states “the BMC updates the preset total maximum output power to the total maximum output power, and transmits a signal of the total maximum output power to the south-bridge chip to trigger the configuration management program to generate the interrupt, so that the interrupt is processed by the interrupt handler to adjust the power consumption of the CPU” and ¶ [0046] states “he BMC 240, then finds the working frequency, the duty cycle, and the number of threads of the CPU 210 to be adjusted from a basic input/output system read-only memory (BIOS ROM) in the table look-up manner “ Also, Fig’s 1,3))
D) when receiving the updated power consumption limit, the BIOS outputting a first system management interrupt to the CPU, (the interrupt is a system management interrupt (SMI), ; ¶ [0014]) and writing the updated power consumption limit into a model-specific register of the CPU; and (¶ [0048] states “A register of the CPU 210 (for example, a model-specific register (MSR)) may be arranged to set the duty cycle and the working frequency of the CPU 210 and turn off the threads of specific APIC IDs.” Also, Fig’s 1,3)
E) after step D), the BIOS notifying the control unit to change the throttling signal from the throttling state to the non-throttling state, so that the CPU operates under restriction of the updated power consumption limit according to the model-specific register. ( ¶ [0031] states that “the interrupt is processed by an interrupt handler to adjust a power consumption of the CPU 210”. Also, Fig’s 1,3)
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Ma and Lu because both references are in the same field of endeavor. Lu’s teaching of throttling a CPU based on updated available power would enhance Ma's system by allowing power supplied to be adapted based on the newly updated available power, thus enhancing power management for the computer system.
As per claims 2, 12, Ma as modified discloses a power management method wherein, in step C), the control unit determines a power differential based on the maximum output power value of the first PSU, and subtracts the power differential from a predefined normal power consumption limit of the CPU to obtain the updated power consumption limit. (¶ [0033] of Lu discloses a mathematical process of subtracting a power wattage from an unhealthy power supply to determine the “total maximum output power”, table 2)
As per claims 3, 13, Ma as modified discloses wherein, in step C), the control unit subtracts a maximum power consumption value of the computer system from the total maximum output power value of the PSU(s) other than the first PSU to obtain a power differential, and adds up the power differential and a predefined normal power consumption limit of the CPU to obtain the updated power consumption limit when the power differential is smaller than zero. (Lu: the output powers of the seven power supplies 220_1 to 220_7 are added up as 150 W*3+100W*3+0W-750 W, to obtain the total maximum output power; ¶ [0033], table 2)
As per claims 4, 14, Ma as modified discloses wherein, in step C), the control unit subtracts a maximum power consumption value of the computer system from the total maximum output power value of the PSU(s) other than the first PSU to obtain a power differential, and subtracts a predetermined buffer value from a sum of the power differential and a predefined normal power consumption limit of the CPU to obtain the updated power consumption limit when the power differential is smaller than zero. (Lu: the output powers of the seven power supplies 220_1 to 220_7 are added up as 150 W*3+100W*3+0W-750 W, to obtain the total maximum output power; ¶ [0033], table 2)
As per claim 5, Ma as modified discloses wherein the control unit is a baseboard management controller (BMC). (Lu: ¶ [0016])
As per claim(s) 6, Ma as modified discloses wherein the control unit includes a baseboard management controller (BMC) and a complex programmable logic device (CPLD); (Lu: BMC and south-brige chip) & (Ma: ¶ 004])
wherein the alert signal is sent to the CPLD, and the throttling signal is sent by the CPLD to the CPU; (Lu: south-bridge chip adjusts the power consumption of the CPU to a preset value; ¶ [0017]) & (Ma: ¶ 004])
wherein step B) includes the CPLD notifying the BMC that the alert signal has changed from the non-alert state to the alert state; wherein, in step C), (LU: The BMC, and used for receiving the detection signal ; ¶ [0016]) & (Ma: ¶ 004])
the BMC computes and sends the updated power consumption limit to the BIOS upon being notified that the alert signal has changed from the non-alert state to the alert state; and wherein step E) includes the BIOS sending a notification to the BMC, thereby causing the BMC to notify the CPLD to change the throttling signal from the throttling state to the non-throttling state. (Lu: the BMC, and used for receiving the detection signal or the total maximum output power and accordingly triggering a configuration management program to generate an interrupt, so that the interrupt is processed by an interrupt handler to adjust a power consumption of the CPU.; ¶ [0016]) & (Ma: ¶ 004])
As per claim(s) 7, Ma as modified discloses further comprising, after step E), steps of: F) the first PSU changing the alert signal from the alert state to the non-alert state when the first PSU is released from the predefined abnormal condition; and G) when detecting that the alert signal sent by the first PSU has changed from the alert state to the non-alert state, the control unit notifying the BIOS to send a second system management interrupt to the CPU, and to write a predefined normal power consumption limit into the model-specific register of the CPU. (Lu: ¶ [0031] states that “the interrupt is processed by an interrupt handler to adjust a power consumption of the CPU 210”. Also, Fig’s 1,3) & (Ma: ¶ [004] states “triggering Central Processing Unit (CPU) throttling by a Power Supply Unit (PSU) Alert signal. When the PSU has faults such as over-temperature or over-current alerts, the PSU Alert signal is pulled down. Once detecting that the PSU Alert signal is pulled down, a Complex Programmable Logic Device (CPLD) triggers CPU throttling, and the CPU in the server will then operate at a lower frequency, thereby significantly reducing system power consumption.” AND (the interrupt is a system management interrupt (SMI), ; ¶ [0014]) and writing the updated power consumption limit into a model-specific register of the CPU; and (¶ [0048] states “A register of the CPU 210 (for example, a model-specific register (MSR)) may be arranged to set the duty cycle and the working frequency of the CPU 210 and turn off the threads of specific APIC IDs.” Also, Fig’s 1,3) )
As per claim(s) 8, Ma as modified discloses wherein the control unit includes a baseboard management controller (BMC) and a complex programmable logic device (CPLD), and the alert signal is sent to the CPLD; wherein, in step G), when detecting that the alert signal sent by the first PSU has changed from the alert state to the non-alert state, the CPLD notifies the BMC of the change of the alert signal sent by the first PSU, so that the BMC notifies the BIOS to send the second system management interrupt to the CPU, and to write the predefined normal power consumption limit into the model-specific register of the CPU. (Lu: ¶ [0031] states that “the interrupt is processed by an interrupt handler to adjust a power consumption of the CPU 210”. Also, Fig’s 1,3) & (Ma: ¶ [004] states “triggering Central Processing Unit (CPU) throttling by a Power Supply Unit (PSU) Alert signal. When the PSU has faults such as over-temperature or over-current alerts, the PSU Alert signal is pulled down. Once detecting that the PSU Alert signal is pulled down, a Complex Programmable Logic Device (CPLD) triggers CPU throttling, and the CPU in the server will then operate at a lower frequency, thereby significantly reducing system power consumption.” AND (the interrupt is a system management interrupt (SMI), ; ¶ [0014]) and writing the updated power consumption limit into a model-specific register of the CPU; and (¶ [0048] states “A register of the CPU 210 (for example, a model-specific register (MSR)) may be arranged to set the duty cycle and the working frequency of the CPU 210 and turn off the threads of specific APIC IDs.” Also, Fig’s 1,3) )
As per claim(s) 9, Ma as modified discloses further comprising, after step E), steps of: F) the first PSU changing the alert signal from the alert state to the non-alert state when the first PSU is released from the predefined abnormal condition; and G) when detecting that the alert signal sent by the first PSU has changed from the alert state to the non-alert state, the control unit monitoring operation of each of the PSUs, and, when determining that none of the PSUs operates in the predefined abnormal condition, notifying the BIOS to send a second system management interrupt to the CPU, and to write a predefined normal power consumption limit into the model-specific register of the CPU. (Lu: ¶ [0031] states that “the interrupt is processed by an interrupt handler to adjust a power consumption of the CPU 210”. Also, Fig’s 1,3) & (Ma: ¶ [004] states “triggering Central Processing Unit (CPU) throttling by a Power Supply Unit (PSU) Alert signal. When the PSU has faults such as over-temperature or over-current alerts, the PSU Alert signal is pulled down. Once detecting that the PSU Alert signal is pulled down, a Complex Programmable Logic Device (CPLD) triggers CPU throttling, and the CPU in the server will then operate at a lower frequency, thereby significantly reducing system power consumption.” AND (the interrupt is a system management interrupt (SMI), ; ¶ [0014]) and writing the updated power consumption limit into a model-specific register of the CPU; and (¶ [0048] states “A register of the CPU 210 (for example, a model-specific register (MSR)) may be arranged to set the duty cycle and the working frequency of the CPU 210 and turn off the threads of specific APIC IDs.” Also, Fig’s 1,3) )
As per claim(s) 10, Ma as modified discloses wherein the control unit includes a baseboard management controller (BMC) and a complex programmable logic device (CPLD), and the alert signal is sent to the CPLD; wherein, in step G), when detecting that the alert signal sent by the first PSU has changed from the alert state to the non-alert state, the CPLD causes the BMC to monitor the operation of each of the PSUs; and wherein, in step G), when determining that none of the PSUs operates in the predefined abnormal condition, the BMC notifies the BIOS to send the second system management interrupt to the CPU, and to write the predefined normal power consumption limit into the model-specific register of the CPU. (Lu: ¶ [0031] states that “the interrupt is processed by an interrupt handler to adjust a power consumption of the CPU 210”. Also, Fig’s 1,3) & (Ma: ¶ [004] states “triggering Central Processing Unit (CPU) throttling by a Power Supply Unit (PSU) Alert signal. When the PSU has faults such as over-temperature or over-current alerts, the PSU Alert signal is pulled down. Once detecting that the PSU Alert signal is pulled down, a Complex Programmable Logic Device (CPLD) triggers CPU throttling, and the CPU in the server will then operate at a lower frequency, thereby significantly reducing system power consumption.” AND (the interrupt is a system management interrupt (SMI), ; ¶ [0014]) and writing the updated power consumption limit into a model-specific register of the CPU; and (¶ [0048] states “A register of the CPU 210 (for example, a model-specific register (MSR)) may be arranged to set the duty cycle and the working frequency of the CPU 210 and turn off the threads of specific APIC IDs.” Also, Fig’s 1,3)
As per claim(s) 15, Ma as modified discloses wherein the control unit includes a logic circuit unit that is disposed to receive the alert signal from each of the PSUs and the notification signal from the BIOS, and that is configured to perform logic operations to generate the throttling signal in such a way that the throttling signal is in the non-throttling state when each of the alert signals received from the PSUs is in the non-alert state and the notification signal is in the non-notification state, that the throttling signal is in the throttling state when any of the alert signals received from the PSUs is in the alert state and the notification signal is in the non-notification state, and that the throttling signal is in the non-throttling state when the notification signal is in the notification state. (Lu: ¶ [0031] states that “the interrupt is processed by an interrupt handler to adjust a power consumption of the CPU 210”. Also, Fig’s 1,3) & (Ma: ¶ [004] states “triggering Central Processing Unit (CPU) throttling by a Power Supply Unit (PSU) Alert signal. When the PSU has faults such as over-temperature or over-current alerts, the PSU Alert signal is pulled down. Once detecting that the PSU Alert signal is pulled down, a Complex Programmable Logic Device (CPLD) triggers CPU throttling, and the CPU in the server will then operate at a lower frequency, thereby significantly reducing system power consumption.” AND (the interrupt is a system management interrupt (SMI), ; ¶ [0014]) and writing the updated power consumption limit into a model-specific register of the CPU; and (¶ [0048] states “A register of the CPU 210 (for example, a model-specific register (MSR)) may be arranged to set the duty cycle and the working frequency of the CPU 210 and turn off the threads of specific APIC IDs.” Also, Fig’s 1,3)
As per claim(s) 16, Ma as modified discloses further comprising, after step E), steps of: F) the first PSU changing the alert signal sent thereby from the alert state to the non-alert state when the first PSU is released from the predefined abnormal condition; and G) when detecting that the alert signal sent by the first PSU has changed from the alert state to the non-alert state and that each of the alert signals sent by the PSUs is in the non-alert state, the BIOS sending a second system management interrupt to the CPU, and writing a predefined normal power consumption limit into the model-specific register of the CPU. (Lu: ¶ [0031] states that “the interrupt is processed by an interrupt handler to adjust a power consumption of the CPU 210”. Also, Fig’s 1,3) & (Ma: ¶ [004] states “triggering Central Processing Unit (CPU) throttling by a Power Supply Unit (PSU) Alert signal. When the PSU has faults such as over-temperature or over-current alerts, the PSU Alert signal is pulled down. Once detecting that the PSU Alert signal is pulled down, a Complex Programmable Logic Device (CPLD) triggers CPU throttling, and the CPU in the server will then operate at a lower frequency, thereby significantly reducing system power consumption.” AND (the interrupt is a system management interrupt (SMI), ; ¶ [0014]) and writing the updated power consumption limit into a model-specific register of the CPU; and (¶ [0048] states “A register of the CPU 210 (for example, a model-specific register (MSR)) may be arranged to set the duty cycle and the working frequency of the CPU 210 and turn off the threads of specific APIC IDs.” Also, Fig’s 1,3)
Conclusion
With respect to any newly added or amended claims, applicant should show support in the original disclosure for the new or amended claims. See MPEP §714.02 and § 2163.06. For example, when responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUREL PRIFTI whose telephone number is (571)270-1743. The examiner can normally be reached on M-F 8 a.m.- 6 p.m..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached on 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AUREL PRIFTI/Primary Examiner, Art Unit 2175
Aurel Prifti
Primary Examiner
Art Unit 2175
Tel. (571) 270-1743
Fax (571) 270-2743
aurel.prifti@uspto.gov