Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This is the initial Office action based on the application filed on March 26, 2024.
Claims 1-20 are presently pending in the application have been examined below, of which, claims 1, 8, and 15 are presented in independent form.
Allowable Subject Matter
Claims 2 and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 3-4 and 6-7 are considered allowable by virtue of their dependence on the rewritten allowable independent claims 2 and 5 respectively.
Claims 9-14 and 16-20 are substantially similar to claims 2-7 and objected to under the same rationale set forth in claims 2-7.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0095024 (hereinafter "Ozen”), in view of US 8,219,378 (hereinafter “Koh”), and further in view of US 2004/0255279 (hereinafter “Rawsthorne”).
In the following claim analysis, Applicant’s claim limitations are presented in bold text, the Examiner’s explanations, notes, and remarks are enclosed in square brackets; and emphasized portions are underlined.
As to claim 1, Ozen discloses A computer-implemented method comprising (Ozen, Fig. 5, ¶ 69, n example computer system 500 where a code versions are generated, … a compiler 508 executing on processor 502 generates one or more software kernels using source code 504 and directives 506):
receiving, by one or more processors, a kernel definition comprising a parameterization and code of a set of generators written in a general purpose programming language (Ozen, Fig. 5, ¶ 69, a compiler 508 executing on processor 502 generates one or more software kernels using source code 504 [written in a general purpose programming language] and directives 506 [defines how the kernels are generated]; ¶ 70, compiler 508 generates at least a first software kernel 510, which is an optimized kernel where there is no memory overlap (also referred to herein as no memory aliasing). … compiler 508 generates at least a second software kernel 512, which is an less optimized kernel (e.g., a kernel with fewer optimizations than first software kernel 510) [It is noted that these distinct kernel are generated based on differing optimization assumptions and memory aliasing criteria. Generation of such distinct kernel versions based on differing criteria requires respective kernel-generating logic operative to produce each version. Under the broadest reasonable interpretation, a code generator is code a logic that generates a respective kernel version based on specified parameters or directives. Thus, the respective kernel generating logic associated with the source code 104 and directives corresponds to a set of generators. Further, the directives specifying optimization assumptions and memory aliasing constitutes a parametrization that specifies functions and one or more variables]);
for each generator of the set of generators, performing operations comprising (Ozen, Fig. 5, ¶ 70, a graphics processor such as graphics processor 116 executes or otherwise performs instructions to select from multiple versions of a portion of a program to be performed (e.g., first software kernel 510 and/or second software kernel 512 [It is noted that Ozen generates multiple software kernels from source code using directives, each kernel generation corresponds to operation on a respective generator of the set of generators]):
translating, by the one or more processors, code of the each generator into a first intermediate representation of the each generator (Ozen, ¶ 315, Source code may be compiled offline prior to executing an application or online during execution of an application … compile source code and/or IR code, such as Standard Portable Intermediate Representation (“SPIR-V”) code);
generating, by the one or more processors, a respective binary object of a set of binary objects using the second intermediate representation (Ozen, ¶ 301, device kernel driver 3206 may be configured to compile intermediate representation (“IR”) code into binary code; ¶ 315, compile source code and/or IR code, such as Standard Portable Intermediate Representation (“SPIR-V”) code, into binary code; ¶ 329, native object code for a host and PTX or binary code for a device may be linked together … which is a container format used to store object code); and
composing, by the one or more processors, a kernel corresponding to the kernel definition using the set of binary objects (Ozen, ¶ 56, compiler 108 uses source code 104 and directives 106 to generate software kernels 112; Fig. 5, ¶ 70, compiler 508 generates at least a second software kernel 512, which is an less optimized kernel (e.g., a kernel with fewer optimizations than first software kernel 510), where there is possible memory overlap; ¶ 329, inker 3809 links host and device executable code 3807 and 3808 together in executable file 3810 … native object code for a host and PTX or binary code for a device may be linked together in an Executable and Linkable Format (“ELF”) file, which is a container format used to store object code).
Ozen does not appear to explicitly disclose determining, by the one or more processors, a configuration of the each generator using the parameterization and the first intermediate representation; and generating, by the one or more processors, a second intermediate representation using the configuration. However, in an analogous art to the claimed invention in the field of compilation, Koh teaches determining, by the one or more processors, a configuration of the each generator using the parameterization and the first intermediate representation (Koh, col. 24, ln. 19-25, comparer 410 may update the simulation IR based on the one or more manually-identified attributes (block 1354), may update the architecture settings information [that constitutes determining a configuration using both parameters and IR] and/or compiler, compiler settings, and/or operating system information (e.g., information 415) based on the one or more manually-identified attributes [in the parameterization] (block 1356)); and generating, by the one or more processors, a second intermediate representation using the configuration (Koh, col. 2, ln. 33-35, Environment settings and/or IR files may be updated [as a second IR using the configuration]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Ozen with the teaching of Koh. The modification would be obvious because one of ordinary skill in the art would be motivated to allow parameter-driven configuration of IRs to improve adaptability of compiled kernels to varying execution environments.
Ozen as modified does not appear to explicitly disclose caching, by the one or more processors, the intermediate representation. However, in an analogous art to the claimed invention in the field of intermediate representation generation, Rawsthorne teaches caching, by the one or more processors, the intermediate representation (Rawsthorne, ¶ 81, This effectively caches all of the decoding and IR generation performed by the frontend … the translation hints include the IR forest as it exists prior to being optimized).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Ozen as modified with the teaching of Rawsthorne. The modification would be obvious because one of ordinary skill in the art would be motivated to cache IRs to Ozen’s compilation pipeline to reduce redundant IR generation and improve compilation efficiency.
Claim 8 is essentially the same as claim 1 except is set forth the claimed invention as a machine and is rejected with the same reasoning as applied hereinabove in claim 1. Ozen further discloses the claim limitations A machine comprising: one or more processors; and one or more memories storing instructions that, when executed by the one or more processors, cause the machine to perform operations …. (Ozen, claim 19, A computer system comprising: one or more processors and memory storing executable instructions that, if performed by the one or more processors, perform …).
Claim 15 is essentially the same as claim 1 except is set forth the claimed invention as a machine-storage medium and is rejected with the same reasoning as applied hereinabove in claim 1. Ozen further discloses the claim limitations A machine-storage medium including instructions that, when executed by one or more processors of a machine, cause the machine to perform operations …. (Ozen, claim 28, A machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, perform …).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 11,983,624 teaches an auto generation and tuning tool for convolution kernels;
US 2017/0300306 teaches generating an intermediate representation of received source code for compiling or interpreting on the computing device; and
“The Next 700 Accelerated Layers: From Mathematical Expressions of Network Computation Graphs to Accelerated GPU Kernels, Automatically” teaches generating highly optimized kernels for tensor expressions.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAXIN WU whose telephone number is (571) 270-7721. The examiner can normally be reached on M-F (7 am - 11:30 am; 1:30- 5 pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner' s supervisor, Wei Mui can be reached at (571) 272-3708. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAXIN WU/
Primary Examiner, Art Unit 2191