DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Li (Pub. No. US20080082866) in view of Lee (Pub. No. US20210194724)
As per claim 1, Li discloses System on a Chip (SoC), comprising a processor (fig.4, processor), a read and write device (paragraph 30, read and write operation for storing the address of the target/initiator boards via Compact PCI bus) and a controller (fig.4, monitoring unit), wherein the processor is configured to:
write a target instruction to the read and write device (fig.4, Service board 2, receives access information and writes the access information to the memory of a target device); and
stop writing the target instruction to the read and write device and performing another task (paragraph 53, other boards initiating an access to the failed target board may also stop the retry access) in response to detecting that a number of times that the target instruction has not been successfully written to the I2C read and write device consecutively reaches N times, where N>=2 (paragraph 30, lines 13-19, counting retry response of the current access when reaches a retry times threshold);
wherein the read and write device is configured to parse the target instruction, and generate and output an instruction corresponding to the target instruction (paragraph 30, 16-17, providing read and write operation for storing the address of the target board in the monitoring unit and predetermining the retry times threshold); and
wherein the controller is configured to perform a control operation on a connected slave device (fig.4, Service board 2) based on the instruction (paragraph 28, monitors the operation on the bus in real time, acquires and stores the address of the target board).
Li discloses all the limitations as the above but does not explicitly disclose compact PCI of Li is I2C device. However, Lee discloses this (paragraph 124, lines 23-24, NODE-to-NODE through I2C)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Lee with the teaching of Li so as simplifies circuit wiring by using a synchronized clock and shared data line. so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 9, Li discloses an instruction processing method, comprising:
obtaining a number of times that a target instruction (paragraph 28, send the address of a target board when data transmission starts) has not been successfully written to read and write device consecutively (paragraph 30, lines 13-19, counting retry response of the current access when reaches a retry times threshold);
stopping writing the target instruction to the read and write device and performing another task (paragraph 53, other boards initiating an access to the failed target board may also stop the retry access) in response to detecting that the number of times that the target instruction has not been successfully written to the read and write device consecutively reaches N times, where N>=2(paragraph 30, 16-17, providing read and write operation for storing the address of the target board in the monitoring unit and predetermining the retry times threshold); and
rewriting the target instruction to the read and write device in response to receiving an interrupt signal output by the read and write device (paragraph 28, monitors the operation on the bus in real time, acquires and stores the address of the target board, if the times of the retry response of a target board exceed a predefined threshold, generates a reset signal to the target board to make the target board operate normally).
Li discloses all the limitations as the above but does not explicitly disclose compact PCI of Li is I2C device. However, Lee discloses this Li discloses all the limitations as the above but does not explicitly disclose compact PCI of Li is I2C device. However, Lee discloses this (paragraph 124, lines 23-24, NODE-to-NODE through I2C)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Lee with the teaching of Li so as simplifies circuit wiring by using a synchronized clock and shared data line. so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 12, Li discloses processor (fig.4, processor), comprising:
an acquiring circuitry configured to obtain a number of times that a target instruction has not been successfully written to a read and write device consecutively (paragraph 30, read and write operation for storing the address of the target/initiate boards via Compact PCI bus); and
a performing circuitry configured to: stop writing the target instruction to the read and write device and perform another task (paragraph 53, other boards initiating an access to the failed target board may also stop the retry access) in response to detecting that the number of times that the target instruction has not been successfully written to the read and write device consecutively reaches N times (paragraph 30, 16-17, providing read and write operation for storing the address of the target board in the monitoring unit and predetermining the retry times threshold); and
rewrite the target instruction to the read and write device in response to receiving an interrupt signal output by the read and write device (paragraph 28, monitors the operation on the bus in real time, acquires and stores the address of the target board, if the times of the retry response of a target board exceed a predefined threshold, generates a reset signal to the target board to make the target board operate normally).
Li discloses all the limitations as the above but does not explicitly disclose compact PCI of Li is I2C device. However, Lee discloses this Li discloses all the limitations as the above but does not explicitly disclose compact PCI of Li is I2C device. However, Lee discloses this (paragraph 124, lines 23-24, NODE-to-NODE through I2C)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Lee with the teaching of Li so as simplifies circuit wiring by using a synchronized clock and shared data line. so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claims 2, 15, Li discloses wherein the read and write device comprises an instruction receiving register (paragraph 44, read/write the address from/to the address register), an instruction fetching control module (paragraph 47, PCI interface logic module), and an instruction decoding module (paragraph 51, decoding logic module), wherein the instruction receiving register is configured to receive the target instruction (paragraph 44, line 6, read the address from the address register, locate the failed target board);
wherein the instruction module is configured to output the target instruction to the instruction fetching control module (paragraph 30, read and write operation for storing the address of the target/initiate boards via Compact PCI bus); wherein the instruction fetching control module is configured to cache the target instruction(paragraph 44, line 6, read the address from the address register, locate the failed target board); and wherein the instruction decoding module is configured to decode the target instruction, and generate and output the instruction corresponding to the target instruction(paragraph 36, the decoding logic module is used for comparing a retry times threshold with the times of the retry response of the current access to determine whether the times of the retry response exceed the retry times threshold and generating a reset signal).
Li discloses all the limitations as the above but does not explicitly disclose an instruction cache First-In-First-Out (FIFO) module. However, Lee discloses this (paragraph 209, master device updates its cache by reading the CSR Registers periodically, passing the updated CSR Register data to I2C/I3C slave cache in the destination node.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Lee with the teaching of Li so as simplifies circuit wiring by using a synchronized clock and shared data line. so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claims 3, 16, Li discloses wherein the processor is configured to: obtain an operation state of the instruction receiving register (paragraph 53, reads the address of the target board being accessed from the address register and queries for the failed board corresponding to the address to determine which board fails);
write the target instruction to the instruction receiving register in response to detecting that the instruction receiving register is in an idle state (fig.4, Service board 2, receives access information and writes the access information to the memory of a target device); and
stop writing the target instruction to the instruction receiving register (paragraph 47, PCI interface logic module), in response to detecting that the instruction receiving register is in a busy state (paragraph 8, determined that the access module operates normally, otherwise, the expiring event is performed as a response for the access module.) and that a number of times that the instruction receiving register is in the busy state consecutively reaches N times (paragraph 53, other boards initiating an access to the failed target board may also stop the retry access).
As per claims 4, 17, Li discloses wherein the processor is configured to consecutively write to the instruction receiving register at least two target instructions that meet a preset condition (paragraph 9, lines 9-10, the preset operations corresponding to an expiring event only includes such functions as response, notification and failure record); and wherein the I2C read and write device is further configured to merge the at least two target instructions that meet the preset condition (paragraph 9, lines 9-10, the preset operations corresponding to an expiring event only includes such functions as response).
As per claims 5, 18, Li discloses wherein the preset condition comprises any one of the following: register addresses pointed by the at least two target instructions being adjacent (paragraph 34, PCI interface logic module acquires the address of a target board from the Compact PCI bus, writes the address into the address register); or a difference between the register addresses pointed by the at least two target instructions reaching a predetermined distance (paragraph 21, determining that the times of the retry response of the target board exceed a predetermined retry times threshold, the monitoring units sends a reset signal to the target board to reset the target board so as to restore the normal operation of the target board).
As per claim 6, Lee discloses the SoC further comprising a data cache configured to cache data returned by the slave device (paragraph 209, master device updates its cache by reading the CSR Registers periodically, passing the updated CSR Register data to I2C/I3C slave cache in the destination node.)
As per claims 7, 20, Li discloses the SoC further comprising an interrupt signal merging module configured to merge interrupt signals generated by the read and write device and the controller to obtain a merged signal, and output the merged signal to the processor (paragraph 30, lines 17-30, the monitoring unit and is used for providing read and write operation for storing the address of the target board in the monitoring unit and predetermining the retry times threshold, reading the address of the target board based on the interrupt signal sent by the monitoring unit.)
As per claims 8, 19, Li discloses wherein the target instruction comprises at least one of the following: a register data field of the slave device (paragraph 34, the address of a target board), a register address field of the slave device, an identity field of the slave device, a data address format field of the slave device, an I2C read and write direction field, or an access mode field (paragraph 34, the address register, determines whether a retry response is generated for the current access on the Compact PCI bus).
As per claim 10, Li discloses the instruction processing method further comprising: consecutively writing to the I2C read and write device at least two target instructions that meet a preset condition, wherein the preset condition comprises any one of the following: register addresses pointed by the at least two target instructions being adjacent (paragraph 34, PCI interface logic module acquires the address of a target board from the Compact PCI bus, writes the address into the address register); or a difference between the register addresses pointed by the at least two target instructions reaching a predetermined distance(paragraph 21, determining that the times of the retry response of the target board exceed a predetermined retry times threshold, the monitoring units sends a reset signal to the target board to reset the target board so as to restore the normal operation of the target board).
As per claim 11, Li discloses the instruction processing method further comprising: reading data returned for M times by a slave device in response to detecting that a number of times that the data is returned by the slave device reaches a preset number M, wherein M>=2 (paragraph 44, add one counting unit to the times of the retry response of the target board in the retry counter corresponding to the target board; when the times of the retry response in the retry counter reaches a threshold.)
As per claim 13, Li discloses wherein the I2C read and write device is configured to parse the target instruction, and generate and output an instruction corresponding to the target instruction (paragraph 30, 16-17, providing read and write operation for storing the address of the target board in the monitoring unit and predetermining the retry times threshold)
As per claim 14, Li discloses wherein the instruction is transmitted to a controller configured to perform a control operation on a connected slave device based on the instruction (paragraph 6, lines 3-6, The CPU of Service board 1 initiates an access to the memory of Service board 2, access information of Service board 1 is transmitted to the Compact PCI bus through the host bridge and the PCI to PCI (P2P) bridge of Service board 1).
3. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Inogai [Pub. No. US20050108446] discloses accesses a transfer source and a transfer destination of a DMA transfer via a bus.
Riley et al. [Pub. No. US20020073258] discloses he PCI specification, including Registered PCI, all PCI devices shall implement a base set of configuration registers.
Conclusion
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV].
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/K. T. H./
Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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