DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 2, 2026 has been entered.
Response to Amendment
With respect to Applicant’s amendment to Claim 18 in regards to minor informalities, objections with respect to the same has been withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, 8-9, 11, 15 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US PGPUB 2022/0222011) in view of Mori et al. (US PGPUB 2004/0260874).
With regard to Claim 1, Choi teaches a computing system, comprising:
a host device configured to (Fig. 1: Host 20):
generate a first command including information associated with operations to be requested ([0029] “The host controller 24 may store a plurality of write commands in the host write buffer 26 to generate a merged write command by merging a plurality of write commands generated by the host 20.”),
the information including a first information portion associated with a first operation of the operations and a second information portion associated with a second operation to be requested subsequent to the first operation ([0040] “the host 20 of FIG. 1 may include the file system 110, the host write buffer 120, and the data transmission manager 130 of FIG. 2, and the storage device 40 of FIG. 1 may include the storage device 140 of FIG. 2.” [0051] “When the host write buffer 200 receives the third write command WC3 larger than a remaining space of the first host write buffer 210, a third_1 write command WC3_1 may be stored in the first host write buffer 210 and a third_2 write command WC3_2 may be stored in the second host write buffer 220.” [0052] “The storage system may generate a first merged write command MWC1 by merging the first write command WC1, the second write command WC2, and the third_1 write command WC3_1, stored in the first host write buffer 210,” wherein the “write command WC1” and “third_1 write command WC3_1” are the “first information portion” and the “second information portion”.); and
output the first command including the first information portion and the second information portion ([0052] “The storage system may transmit the generated first merged write command MWC1 to the storage device through the data transmission manager.”); and
a storage device configured to store data and in communication with the host device (Fig. 1: Storage Device 140),
wherein the storage device is configured to:
receive the first command from the host device ([0076] “When the first merged write command MWC1 is received, the storage device 550 may confirm that the first merged write command MWC1 is a command obtained by merging a plurality of write commands”);
perform the first operation in response to the first command; and perform part of the second operation based on the second information portion in the first command ([0076] “The storage device 550 may divide data corresponding to a write command in the first merged write command MWC1 and store the divided data in a non-volatile memory,” wherein the “write command WC1”, i.e. the “first information portion”, and the “third_1 write command WC3_1”, i.e. the “second information portion”, write operations are performed in response to the received commands.),
prior to receiving a second command associated with a remaining operation other than the part of the second operation ([0051] “a third_2 write command WC3_2 may be stored in the second host write buffer 220,” wherein the “third_2 write command WC3_2” is the “remaining operation” and further wherein storage of the divided data including “WC3_1”, i.e. the “second information portion”, occurs prior to receiving a further merged write command, i.e. “a second command”, comprising the data being accumulated in the “second host write buffer 220.” [0053] “Referring to FIG. 3D, the host write buffer 200 may store a fourth write command WC4 received from the file system in the second host write buffer 220 while the first host write buffer 210 performs a write command merge and transmits the first merged write command MWC1. The storage system may use the first host write buffer 210 and the second host write buffer 220, and transmit the first merged write command MWC1 from the first host write buffer 210 and simultaneously receive other write commands from the file system through the second host write buffer 220 to store and merge the other write commands,” wherein a second merged write command, i.e. “second command”, comprising at least the write commands “WC3_2” and “WC4” is generated, transmitted and performed by the storage device in the same manner as described above in regards to the first merged write command “MWC1”.).
With further regard to claim 1, Choi does not teach the generation of the second command after receiving the response to the first command as described in claim 1. Mori teaches
wherein the host device is configured to generate the second command after receiving a response to the first command from the storage device ([0125] “Receiving the response of completion of command processing from the channel control unit 13, the host OS 7 may generate and transmit the second sub command 19B,” wherein Fig. 1 shows that “Channel Control Unit 13” is associated with “Disk Array Apparatus 3”, i.e. “the storage device”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the system as disclosed by Choi with the generation of the second command after receiving the response to the first command as taught by Mori since such enforcement of command ordering is known to enhance data security and ensure that the memory state is maintained correctly.
With regard to Claim 3, Choi in view of Mori teaches all the limitations of Claim 1 as described above. Choi further teaches wherein the second information portion includes one or more of a logical address corresponding to the second operation, a length of the logical address, a type of the second operation, identification information of a storage area desired to be accessed during the second operation, or identification information of the host device ([0055] “when the merged write commands have consecutive logical block addresses, there is no need to operate separate metadata… metadata may include a logical block address and length information of a write command,” wherein when the previously indicated write commands, i.e. “WC1”, “WC2” and “WC3_1”, are consecutive then the write commands themselves, i.e. “WC3_1”, include metadata such as the “logical address” and “length”.).
With regard to Claim 4, Choi in view of Mori teaches all the limitations of Claim 3 as described above. Choi further teaches wherein the storage device comprises:
a memory device configured to store a map table including mapping relationships between logical addresses provided from the host device and physical addresses of the memory device ([0026] “The host 20 and the storage device 30 may be connected to each other according to an interface protocol defined in a universal flash storage (UFS) specification, and accordingly, the storage device 30 may be a UFS storage device and the host 20 may be a UFS host.” [0118] “The UFS device controller 2210 may include a flash translation layer (FTL) and, by using address mapping information of the FTL, may convert a logical data address, for example, a logical block address (LBA), which is transferred from the UFS host 2100, into a physical data address, for example, a physical block address (PBA).”); and
a buffer memory configured to temporarily store data provided from the host device or data read from the memory device (Fig. 14: Device Memory 2240. [0120] “The UFS device controller 2210 may temporarily store the received user data in the device memory 2240.” [0121] “The UFS device controller 2210 having received the data read command may read the user data from the non-volatile storage 2220, based on the data read command, and may temporarily store the read user data in the device memory 2240.”).
With regard to Claim 5, Choi in view of Mori teaches all the limitations of Claim 4 as described above. Choi further teaches wherein, in a case that the second operation is a read operation, the storage device obtains a physical address mapped to the logical address corresponding to the second operation from the map table based on the second information portion ([0121] “when the UFS host 2100 intends to read the user data stored in the UFS device 2200, the UFS host 2100 may transmit a data read command to the UFS device 2200. The UFS device controller 2210 having received the data read command may read the user data from the non-volatile storage 2220.” [0118] “The UFS device controller 2210 may include a flash translation layer (FTL) and, by using address mapping information of the FTL, may convert a logical data address, for example, a logical block address (LBA), which is transferred from the UFS host 2100, into a physical data address, for example, a physical block address (PBA).”).
With regard to Claim 6, Choi in view of Mori teaches all the limitations of Claim 5 as described above. Choi further teaches wherein the storage device is configured to read data corresponding to the second operation from the memory device based on the obtained physical address and store the read data in the buffer memory ([0121] “when the UFS host 2100 intends to read the user data stored in the UFS device 2200, the UFS host 2100 may transmit a data read command to the UFS device 2200. The UFS device controller 2210 having received the data read command may read the user data from the non-volatile storage 2220, based on the data read command, and may temporarily store the read user data in the device memory 2240.”).
With regard to Claim 8, Choi in view of Mori teaches all the limitations of Claim 4 as described above. Choi further teaches wherein, in a case that the second operation is a write operation, the storage device allocates a buffer area in which data corresponding to the second operation is to be temporarily stored in the buffer memory ([0120] “when the UFS host 2100 intends to store user data in the UFS device 2200, the UFS host 2100 may transmit a data storage command to the UFS device 2200… The UFS device controller 2210 may temporarily store the received user data in the device memory 2240 and, based on the address mapping information of the FTL, may store the user data temporarily stored in the device memory 2240 in a selected location of the non-volatile storage 2220.”).
With regard to Claim 9, Choi in view of Mori teaches all the limitations of Claim 1 as described above. Choi further teaches wherein the storage device is configured to perform the first operation and the part of the second operation and then transmit the response to the first command to the host device ([0119] “When a command from the UFS host 2100 is input to the UFS device 2200 through the UIC layer 2250, the UFS device controller 2210 may perform an operation according to the input command, and when the operation is completed, the UFS device controller 2210 may transmit a completion response to the UFS host 2100.”).
With regard to Claim 11, Choi teaches a method of operating a computing system, comprising:
generating, by a host device, a first command including information associated with operations to be requested ([0029] “The host controller 24 may store a plurality of write commands in the host write buffer 26 to generate a merged write command by merging a plurality of write commands generated by the host 20.”),
the information including a first information portion associated with a first operation and a second information portion associated with a second operation to be requested subsequent to the first operation ([0040] “the host 20 of FIG. 1 may include the file system 110, the host write buffer 120, and the data transmission manager 130 of FIG. 2, and the storage device 40 of FIG. 1 may include the storage device 140 of FIG. 2.” [0051] “When the host write buffer 200 receives the third write command WC3 larger than a remaining space of the first host write buffer 210, a third_1 write command WC3_1 may be stored in the first host write buffer 210 and a third_2 write command WC3_2 may be stored in the second host write buffer 220.” [0052] “The storage system may generate a first merged write command MWC1 by merging the first write command WC1, the second write command WC2, and the third_1 write command WC3_1, stored in the first host write buffer 210,” wherein the “write command WC1” and “third_1 write command WC3_1” are the “first information portion” and the “second information portion”.);
transmitting, by the host device, the first command to a storage device that stores data ([0052] “The storage system may transmit the generated first merged write command MWC1 to the storage device through the data transmission manager.”);
performing, by the storage device, the first operation in response to the first command; and performing, by the storage device, part of the second operation based on the second information portion in response to the first command ([0076] “The storage device 550 may divide data corresponding to a write command in the first merged write command MWC1 and store the divided data in a non-volatile memory,” wherein the “write command WC1”, i.e. the “first information portion”, and the “third_1 write command WC3_1”, i.e. the “second information portion”, write operations are performed in response to the received commands.),
prior to receiving a second command associated with a remaining operation other than the part of the second operation ([0051] “a third_2 write command WC3_2 may be stored in the second host write buffer 220,” wherein the “third_2 write command WC3_2” is the “remaining operation” and further wherein storage of the divided data including “WC3_1”, i.e. the “second information portion”, occurs prior to receiving a further merged write command, i.e. “a second command”, comprising the data being accumulated in the “second host write buffer 220.”);
transmitting, by the storage device, a response to the first command to the host device ([0119] “When a command from the UFS host 2100 is input to the UFS device 2200 through the UIC layer 2250, the UFS device controller 2210 may perform an operation according to the input command, and when the operation is completed, the UFS device controller 2210 may transmit a completion response to the UFS host 2100.”);
generating, by the host device, the second command including the second information portion; transmitting, by the host device, the second command to the storage device; and performing, by the storage device, a remaining operation other than the part of the second operation in response to the second command ([0051] “a third_2 write command WC3_2 may be stored in the second host write buffer 220.” [0053] “Referring to FIG. 3D, the host write buffer 200 may store a fourth write command WC4 received from the file system in the second host write buffer 220 while the first host write buffer 210 performs a write command merge and transmits the first merged write command MWC1. The storage system may use the first host write buffer 210 and the second host write buffer 220, and transmit the first merged write command MWC1 from the first host write buffer 210 and simultaneously receive other write commands from the file system through the second host write buffer 220 to store and merge the other write commands,” wherein a second merged write command, i.e. “second command”, comprising at least the write commands “WC3_2” and “WC4” is generated, transmitted and performed by the storage device in the same manner as described above in regards to the first merged write command “MWC1”.).
With further regard to claim 11, Choi does not teach the generation of the second command after receiving the response to the first command as described in claim 11. Mori teaches
generating, by the host device, the second command including the second information portion after receiving the response to the first command ([0125] “Receiving the response of completion of command processing from the channel control unit 13, the host OS 7 may generate and transmit the second sub command 19B,” wherein Fig. 1 shows that “Channel Control Unit 13” is associated with “Disk Array Apparatus 3”, i.e. “the storage device”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the method as disclosed by Choi with the generation of the second command after receiving the response to the first command as taught by Mori since such enforcement of command ordering is known to enhance data security and ensure that the memory state is maintained correctly.
With regard to Claim 15, Choi in view of Mori teaches all the limitations of Claim 11 as described above. Choi further teaches wherein performing the part of the second operation comprises:
mapping a physical address to a logical address corresponding to the second operation in response to the second operation in a case that the second operation is a write operation ([0026] “The host 20 and the storage device 30 may be connected to each other according to an interface protocol defined in a universal flash storage (UFS) specification, and accordingly, the storage device 30 may be a UFS storage device and the host 20 may be a UFS host.” [0118] “The UFS device controller 2210 may include a flash translation layer (FTL) and, by using address mapping information of the FTL, may convert a logical data address, for example, a logical block address (LBA), which is transferred from the UFS host 2100, into a physical data address, for example, a physical block address (PBA).” [0120] “when the UFS host 2100 intends to store user data in the UFS device 2200…”); and
allocating a buffer area in which data corresponding to the second operation is temporarily stored ([0120] “when the UFS host 2100 intends to store user data in the UFS device 2200, the UFS host 2100 may transmit a data storage command to the UFS device 2200… The UFS device controller 2210 may temporarily store the received user data in the device memory 2240 and, based on the address mapping information of the FTL, may store the user data temporarily stored in the device memory 2240 in a selected location of the non-volatile storage 2220.”).
With regard to Claim 17, Choi teaches a computing system, comprising:
a host device configured to (Fig. 1: Host 20):
insert a plurality of second information portions associated with a plurality of second operations into a first command for requesting a first operation ([0029] “The host controller 24 may store a plurality of write commands in the host write buffer 26 to generate a merged write command by merging a plurality of write commands generated by the host 20.” [0040] “the host 20 of FIG. 1 may include the file system 110, the host write buffer 120, and the data transmission manager 130 of FIG. 2, and the storage device 40 of FIG. 1 may include the storage device 140 of FIG. 2.” [0051] “When the host write buffer 200 receives the third write command WC3 larger than a remaining space of the first host write buffer 210, a third_1 write command WC3_1 may be stored in the first host write buffer 210 and a third_2 write command WC3_2 may be stored in the second host write buffer 220.” [0052] “The storage system may generate a first merged write command MWC1 by merging the first write command WC1, the second write command WC2, and the third_1 write command WC3_1, stored in the first host write buffer 210,” wherein the “write command WC1” and “third_1 write command WC3_1” are the “first information portion” and the “second information portion”.); and
output the first command including the plurality of second information portions ([0052] “The storage system may transmit the generated first merged write command MWC1 to the storage device through the data transmission manager.”); and
a storage device coupled in communication with the host device (Fig. 1: Storage Device 140), and
configured to:
receive the first command from the host device ([0076] “When the first merged write command MWC1 is received, the storage device 550 may confirm that the first merged write command MWC1 is a command obtained by merging a plurality of write commands”);
perform the first operation in response to the first command; and perform respective parts of the plurality of second operations based on the plurality of second information portions in the first command ([0076] “The storage device 550 may divide data corresponding to a write command in the first merged write command MWC1 and store the divided data in a non-volatile memory,” wherein the “write command WC1”, i.e. the “first information portion”, and the “third_1 write command WC3_1”, i.e. the “second information portion”, write operations are performed in response to the received commands.),
prior to receiving a plurality of second commands associated with remaining operations other than the respective parts of the plurality of second operations ([0051] “a third_2 write command WC3_2 may be stored in the second host write buffer 220,” wherein the “third_2 write command WC3_2” is one of the “remaining operations” and further wherein storage of the divided data including “WC3_1”, i.e. the “second information portions”, occurs prior to receiving a further merged write commands, i.e. “second commands”, comprising the data being accumulated in the “second host write buffer 220.” [0053] “Referring to FIG. 3D, the host write buffer 200 may store a fourth write command WC4 received from the file system in the second host write buffer 220 while the first host write buffer 210 performs a write command merge and transmits the first merged write command MWC1. The storage system may use the first host write buffer 210 and the second host write buffer 220, and transmit the first merged write command MWC1 from the first host write buffer 210 and simultaneously receive other write commands from the file system through the second host write buffer 220 to store and merge the other write commands,” wherein a second merged write command, i.e. “second commands”, comprising at least the write commands “WC3_2” and “WC4” is generated, transmitted and performed by the storage device in the same manner as described above in regards to the first merged write command “MWC1”.).
With further regard to claim 17, Choi does not teach the generation of the second command after receiving the response to the first command as described in claim 17. Mori teaches
wherein the host device is configured to generate the plurality of second commands after receiving a response to the first command from the storage device ([0125] “Receiving the response of completion of command processing from the channel control unit 13, the host OS 7 may generate and transmit the second sub command 19B,” wherein Fig. 1 shows that “Channel Control Unit 13” is associated with “Disk Array Apparatus 3”, i.e. “the storage device”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the system as disclosed by Choi with the generation of the second command after receiving the response to the first command as taught by Mori since such enforcement of command ordering is known to enhance data security and ensure that the memory state is maintained correctly.
With regard to Claim 18, Choi in view of Mori teaches all the limitations of Claim 17 as described above. Choi further teaches wherein the host device is configured to:
receive the response to the first command from the storage device ([0119] “When a command from the UFS host 2100 is input to the UFS device 2200 through the UIC layer 2250, the UFS device controller 2210 may perform an operation according to the input command, and when the operation is completed, the UFS device controller 2210 may transmit a completion response to the UFS host 2100.”);
generate the plurality of second commands for respectively requesting remaining operations, other than the respective parts of the plurality of second operations ([0051] “a third_2 write command WC3_2 may be stored in the second host write buffer 220.” [0053] “Referring to FIG. 3D, the host write buffer 200 may store a fourth write command WC4 received from the file system in the second host write buffer 220 while the first host write buffer 210 performs a write command merge and transmits the first merged write command MWC1. The storage system may use the first host write buffer 210 and the second host write buffer 220, and transmit the first merged write command MWC1 from the first host write buffer 210 and simultaneously receive other write commands from the file system through the second host write buffer 220 to store and merge the other write commands,” wherein a second merged write command, i.e. “second command”, comprising at least the write commands “WC3_2” and “WC4” is generated, transmitted and performed by the storage device in the same manner as described above in regards to the first merged write command “MWC1”.); and
sequentially transmit the plurality of second commands to the storage device ([0122] “The UFS host 2100 may store commands, which is to be transmitted to the UFS device 2200, in the UFS host register 2111 capable of functioning as a command queue according to an order, and may transmit the commands to the UFS device 2200 in the order.”).
With regard to Claim 19, Choi in view of Mori teaches all the limitations of Claim 18 as described above. Choi further teaches wherein the storage device is configured to sequentially perform remaining operations, other than the respective parts of the plurality of second operations, among the plurality of second operations in response to the plurality of second commands ([0122] “the UFS host 2100 may transmit the next command on standby in the command queue to the UFS device 2200, and thus, the UFS device 2200 may also receive the next command from the UFS host 2100 even while processing the previously transmitted command. The maximum number of commands capable of being stored in the command queue (that is, a queue depth) may be, for example, 32. In addition, the command queue may be implemented by a circular queue type in which a start and an end of a command sequence stored in a queue are respectively indicated by a head pointer and a tail pointer.”).
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Mori as applied to Claims 1 and 11 above, and further in view of Lee (US PGPUB 2022/0091757).
With regard to claim 2, Choi in view of Mori teaches all the limitations of claim 1 as described above. Choi in view of Mori does not teach the command fields as described in claim 2. Lee teaches wherein:
the first command comprises a basic header segment, transaction specific fields, and an extra header segment (EHS) ([0007] “a memory controller configured to receive a command protocol component… including a host side protection message requesting data from a host to be written in the protected memory block… wherein the command protocol component comprises: a basic header segment… a transaction specific field including a value for identifying a type of the protocol components; and an extra header segment that is a header segment different from the basic header segment and is configured to include the host side protection message,” see also Fig. 14 of Choi.); and
the host device is configured to include the first information portion in the basic header segment and the transaction specific fields ([0120] “Referring to FIG. 6, the basic header segment 61 may include a transaction type, flags, a logical unit number (LUN), a task tag, an initiator ID, a command set type, a query function/task management function (Query Function, Task Manag. Function), a response, a status, a total extra header segment length (Total EHS Length), device information, and a data segment length.” [0121] “An example of the transaction type according to the type of the PIU is shown in [Table 1] below,” see also Table 1 below Paragraph [0121].) and
include the second information portion in the extra header segment ([0116] “The extra header segment 63 may be an area capable of additionally storing data when sufficient information may not be included in the basic header segment 61.” [0196] “The extra header segment may include the replay protection block message. The replay protection block message may include a message indicating that the command PIU is a PIU instructing the replay protection block write operation.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the system as disclosed by Choi in view of Mori with the command fields as taught by Lee in order “to provide a data storage device and a method of operating the data storage device with an improved security function” (Lee [0013]).
With regard to Claim 12, this claim is equivalent in scope to Claim 2 rejected above, merely having a different independent claim type, and as such Claim 12 is rejected under the same grounds and for the same reasons as discussed above with regard to Claim 2.
Claims 7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Mori as applied to Claims 1 and 4 above, and further in view of Chen (US PGPUB 2022/0229788).
With regard to Claim 7, Choi in view of Mori teaches all the limitations of claim 4 as described above. Choi in view of Mori does not teach the updating of the map table as described in claim 7. Chen teaches
wherein, in a case that the second operation is a write operation, the storage device updates the map table by mapping a physical address to the logical address corresponding to the second operation ([0022] “The memory controller 110 receives the plurality of host commands and the logical addresses, and translates the plurality of host commands into memory operating commands… and further controls the NV memory 120 with the operating commands to perform reading or writing/programing upon the memory units or data pages of specific physical addresses within the NV memory 120, where the physical addresses correspond to the logical addresses. For example, the memory controller 110 may generate or update at least one logical-to-physical (H2F) address mapping table.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the system as disclosed by Choi in view of Mori with the updating of the map table as taught by Chen in order “to manage the relationship between the physical addresses and the logical addresses” (Chen [0022]).
With regard to Claim 10, Choi in view of Mori teaches all the limitations of claim 1 as described above. Choi in view of Mori does not teach the error determination as described in claim 10. Chen teaches wherein the storage device is configured to:
determine whether an error is expected to occur during the second operation based on the second information portion; and transmit information about the error to the host device upon determination that the error is expected to occur ([0036] “Regarding any of the responses (e.g. the UART responses) from the memory device 100 to the host device 50, the error code (labeled ‘ERR Code’ for brevity) may represent a fail code.” [0041] “In Step S12B, the host device 50… can send the data-input command such as the ‘Data In’ command… to the memory device 100 through the UART connection.” [0043] “In Step S13B, the memory device 100… can check whether any error occurs. If Yes, Step S18 is entered.” [0053] “In Step S18, the memory device 100… can send the ready-for-command-receiving command such as the ‘Ready for CMD’ command… to the host device 50 through the UART connection.” [0035] “’Ready for CMD’ command… where the fourth argument Arg4 of this command may carry an error (ERR) code… when there is a need.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the system as disclosed by Choi in view of Mori with the error determination as taught by Chen in order to “indicate an error such as data checksum failure, command execution failure, etc.” (Chen [0036]).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Mori as applied to Claim 11 above, and further in view of Byun (US PGPUB 2021/0026778).
With regard to Claim 13, Choi in view of Mori teaches all the limitations of Claim 11 as described above. Choi further teaches wherein performing the part of the second operation comprises:
translating a logical address corresponding to the second operation into a physical address mapped to the logical address based on the second information portion in response to the second operation that is a read operation ([0121] “when the UFS host 2100 intends to read the user data stored in the UFS device 2200, the UFS host 2100 may transmit a data read command to the UFS device 2200. The UFS device controller 2210 having received the data read command may read the user data from the non-volatile storage 2220.” [0118] “The UFS device controller 2210 may include a flash translation layer (FTL) and, by using address mapping information of the FTL, may convert a logical data address, for example, a logical block address (LBA), which is transferred from the UFS host 2100, into a physical data address, for example, a physical block address (PBA).”).
With further regard to claim 13, Choi in view of Mori does not teach the prefetching as described in claim 13. Byun teaches
prefetching data corresponding to the second operation based on the physical address ([0020] “The controller may determine that a sequential prefetch operation may be performable when the number of the first consecutive physical addresses may be less than the consecutive physical address number.” [0022] “The controller may perform the prefetch operation while the sequential read operation may be performed in an interleaving manner.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the method as disclosed by Choi in view of Mori with the prefetching as taught by Byun in order to “improve performance of the read operation of the memory system and prevent read disturbance” (Byun [0009]).
With regard to Claim 14, Choi in view of Mori and Byun teaches all the limitations of Claim 13 as described above. Byun further teaches wherein performing the remaining operation comprises: transmitting the prefetched data to the host device ([0023] “The controller may transmit prefetched data, which may be a result of the sequential prefetch operation, to the host when a subsequent read request for requesting the prefetched data may be received.”)
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Mori as applied to Claim 15 above, and further in view of Kim (US PGPUB 2019/0278512).
With regard to Claim 16, Choi in view of Mori teaches all the limitations of Claim 15 as described above. Choi further teaches wherein performing the remaining operation comprises:
receiving the data corresponding to the second operation from the host device; and
storing the data corresponding to the second operation in the buffer area ([0120] “when the UFS host 2100 intends to store user data in the UFS device 2200, the UFS host 2100 may transmit a data storage command to the UFS device 2200… The UFS device controller 2210 may temporarily store the received user data in the device memory 2240 and, based on the address mapping information of the FTL, may store the user data temporarily stored in the device memory 2240 in a selected location of the non-volatile storage 2220.”).
With further regard to claim 16, Choi in view of Mori does not teach the flush request as described in claim 16. Kim teaches
storing the data corresponding to the second operation, stored in the buffer area, into a storage area corresponding to the physical address in response to a flush request of the host device ([0109] “When a flush request FRQ is received from the host, the request receiving circuit 1201 of the memory controller 1200 may generate a buffer control signal CTR_BFF and transfer the buffer control signal CTR_BFF to the write buffer 1207. The write buffer 1207 may first output write data corresponding to the received flush request FRQ to the memory device 1100 in response to the buffer control signal CTR_BFF.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the method as disclosed by Choi in view of Mori with the flush request as taught by Kim for purposes of “improving the operational reliability of a memory device” (Kim [0175]).
Response to Arguments
Applicant's arguments, see Pages 7-11 of the Remarks filed 3/2/2026, with respect to the rejections under 35 U.S.C. 103 of Claims 1-19 have been fully considered but they are not persuasive. With respect to the Applicant’s argument that the newly amended language of Claims 1, 11 and 17 is not taught by the previously cited prior art, this argument has been fully considered but is moot in view of the newly cited Mori reference as discussed above in the respective rejections.
With respect to the Applicant’s arguments, Pages 11-13 of the Remarks, that the features of the remaining claims are not taught by the cited prior art, the Office respectfully disagrees. These arguments rely upon the arguments as presented in relation to Claims 1, 11 and 17 and as such the Office directs the Applicant to the response above regarding these arguments.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is as follows:
Gardner (US Patent 6,976,186) discloses a data mirror method and system wherein synchronization is maintained between data mirroring sites ensuring that all mirrored storage devices acknowledge receipt of a previous I/O request from an application before the application may generate the next I/O request.
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/NICHOLAS J SIMONETTI/ Primary Examiner, Art Unit 2137 April 18, 2026
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