DETAILED ACTION
This office action has been issued in response to communications received on 3/30/2026. Claims 1, 5, 10, 17 and 19 were amended. Claim 9 was cancelled and new claim 21 was added. Claims 1-8 and 10-21 are presented for examination. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s cancellation of claim 9 is sufficient to overcome the objection to the aforementioned claim. Accordingly, the objection to claim 9 is withdrawn.
Applicant’s amendments to claim 1 adding “packer used in a modular data processing chip” are insufficient to overcome the rejection of the aforementioned claim under 35 USC 101 for being directed to software per se. This is because the new claim phrase does not specify that the modular data processing chip is PART of the apparatus – the claim only specifies that the packer is used in the processing chip. The Examiner recommends tweaking the claim language to indicate that the apparatus comprises the modular data processing chip. Appropriate clarification/correction is required.
Applicant argues on pages 6-7 of the Remarks that Applicant’s Specification indicates that the packer is hardware because there are references to “packing logic block” in paragraph [0023] of Applicant’s Specification as including an integrated circuit block and Figures 2 and 8 show a packer with a packing logic, however the Examiner respectfully disagrees. Claim 1 refers to a packer, not a packing logic block. Figure 2 refers to “packing logic block” and Figure 8 shows that the packer 840 works with the packing logic block 870 only; it does not show that the packing logic block is included within the packer 840. These examples provide support for adding the packing logic block and integrated circuit into claim 1, but do not show that the packer itself should be interpreted as hardware. Consequently, the Examiner recommends adding the integrated circuit into claim 1 or additional hardware.
Applicant’s Remarks regarding the rejection of claims 1-8 and 10-21 under 35 USC 103 have been considered, but were found non-persuasive.
Applicant’s arguments filed 3/30/2026, with respect to the rejection of claims 1-8 and 10-21 under 35 USC § 103(a) have been fully considered but are moot because newly added claim limitations requiring “the packing logic of the first protocol preserved in packing the one or more first flits having the first flit format into the flit container having the second flit format” require new grounds of rejection necessitated by amendments.
The remaining arguments fail to comply with 37 C.F.R. 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
Consequently, the rejection of the claims under 35 U.S.C. 103 is sustained.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-9 are rejected under 35 U.S.C. 101 as being directed to software per se.
Under 35 U.S.C. 101, a claimed invention must fall within one of the four eligible categories of invention (i.e. process, machine, manufacture, or composition of matter) and must not be directed to subject matter encompassing a judicially recognized exception as interpreted by the courts. MPEP § 2106. The four eligible categories of invention include: (1) process which is an act, or a series of acts or steps, (2) machine which is an concrete thing, consisting of parts, or of certain devices and combination of devices, (3) manufacture which is an article produced from raw or prepared materials by giving to these materials new forms, qualities, properties, or combinations, whether by hand labor or by machinery, and (4) composition of matter which is all compositions of two or more substances and all composite articles, whether they be the results of chemical union, or of mechanical mixture, or whether they be gases, fluids, powders or solids. MPEP 2106(I).
Claim 1 is rejected under 35 U.S.C. 101 as not falling within one of the four statutory categories of invention because the claimed invention is directed to software per se. Claim 1 is directed to “an apparatus . . . comprising a packer. While the packer has been amended to indicate that it is used in a data processing chip, there is nothing in the claim to indicate that the data processing chip is part of or included in the apparatus. Neither the claim or the Specification explicitly limit the system claim elements "apparatus” or “packer” to hardware. Consequently, the elements of the system of claim 1 are interpreted as coding/or software and fail to recite any physical device or machine.
Dependent claims 2-9 fail to remedy the deficiencies of the parent claim from which they derive and are accordingly similarly rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 4, 10-11, 14-16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Prasadh (US 2017/0171095) and Reinig (US 2016/0173398).
Regarding claim 1, Prasadh discloses the limitations of claim 1 substantially as follows:
An apparatus for converting flit formatting (paras. [0054], [0069]-[0070]: converting flits) in a data processing network, comprising:
a packer used in a modular data processing chip and configured at a transmit stage of the flit converter to:
pack in accordance with a packing logic of a first protocol one or more first flits having a first flit format into a flit container having a second flit format that is different from the first flit format of the one or more first flits (paras. [0024]-[0025], [0029], [0054]: packing first flits of a first flit protocol of a smaller data format into a phit (i.e. flit container) having a larger data flit format); and
transmit the flit container having the one or more packed first flits across a link layer of a data processing network in accordance with a second protocol that differs from the first protocol (paras. [0029], [0054], [0069]-[0071]: transmitting flits in a phit across a link layer according to a second protocol).
Prasadh does not explicitly disclose the remaining limitations of claim 1 as follows:
the packing logic of the first protocol preserved in packing the one or more first flits having the first flit format into the flit container having the second flit format
However, in the same field of endeavor, Reinig discloses the remaining limitations of claim 1 as follows:
the packing logic of the first protocol preserved in packing the one or more first flits having the first flit format into the flit container having the second flit format (paras. [0017]-[0018], [0052], [0056], [0065] [0020], [0022], [0031]: command encoding for first received flits is not changed (i.e. preserved) when the received flits are merged/converted/packed into different flits (i.e. flit container) of a different length (i.e. second flit format), wherein the command encoding is unchanged, no re-encoding is performed, the packets are not inspected and the burst encoding is not modified)
Prasadh and Reinig are combinable because both are from the same field of endeavor of transmitting flits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to integrate Reinig’s method of packing flits with the format of common internal flits into a physical link transport frame without re-encoding or changing the internal bit-offsets and field structures within the common internal flits with the system of Prasadh in order to decrease latency and power requirements.
Regarding claim 4, Prasadh and Reinig teach the limitations of claim 1.
Prasadh teaches the limitations of claim 4 as follows:
The apparatus of claim 1, wherein the second flit format of the flit container is larger than the first flit format of the one or more flits (paras. [0054], claim 7: packets of the second flit format may be larger flit format than the packets of the first flit format).
Regarding claim 10, Prasadh teaches the limitations substantially as follows:
A method of converting flit formatting in a data processing network, comprising:
converting in accordance with a packing logic of a first protocol one or more flits having a first flit format into a flit container, the flit container having a second flit format different from the first flit format (paras. [0024]-[0025], [0029], [0054], [0069]-[0071]: converting includes packing first flits of a short data format of a first protocol into a phit having a larger data format according to a second protocol); and
transmitting the flit container having the second flit format across a link layer of the data processing network in accordance with a second protocol (paras. [0029], [0054], [0069]-[0071]: transmitting flits in a phit across a link layer according to a second protocol).
Prasadh does not explicitly disclose the remaining limitations of claim 10 as follows:
the packing logic of the first protocol preserved in converting the one or more flits having the first flit format into the flit container having the second flit format
However, in the same field of endeavor, Reinig discloses the remaining limitations of claim 10 as follows:
the packing logic of the first protocol preserved in converting the one or more
flits having the first flit format into the flit container having the second flit format (paras. [0017]-[0018], [0052], [0056], [0065] [0020], [0022], [0031]: command encoding for first received flits is not changed (i.e. preserved) when the received flits are merged/converted/packed into different flits (i.e. flit container) of a different length (i.e. second flit format), wherein the command encoding is unchanged, no re-encoding is performed, the packets are not inspected and the burst encoding is not modified)
Prasadh and Reinig are combinable because both are from the same field of endeavor of transmitting flits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to integrate Reinig’s method of packing flits with the format of common internal flits into a physical link transport frame without re-encoding or changing the internal bit-offsets and field structures within the common internal flits with the system of Prasadh in order to decrease latency and power requirements.
Regarding claim 11, Prasadh and Reinig teach the limitations of claim 10.
Prasadh teaches the limitations of claim 11 as follows:
The method of claim 10, wherein the converting includes packing in accordance with a packing logic of the first protocol the one or more flits into the flit container having the second flit format (paras. [0024]-[0025], [0029], [0054], [0069]-[0071]: converting includes packing first flits of a short data format into a phit having a larger data format according to a second protocol).
Regarding claim 14, Prasadh and Reinig teach the limitations of claim 10.
Prasadh teaches the limitations of claim 14 as follows:
The method of claim 10, further comprising packing multiples of the one or more flits into the flit container (paras. [0025], [0035], [0054], [0069]-[0071]: packing multiple flits into a phit and reassembling the packet by reassembling the flits from the phit).
Regarding claim 15, Prasadh and Reinig teach the limitations of claims 10 and 14.
Prasadh teaches the limitations of claim 15 as follows:
The method of claim 14, further comprising packing n chunks over n sequential cycles of a processor (Prasadh, paras. [0030], [0051], [0054], [0056], [0062]: packing over cycles of an SoC clock/processor).
Regarding claim 16, Prasadh and Reinig teach the limitations of claim 10.
Prasadh teaches the limitations of claim 16 as follows:
The method of claim 10, further comprising:
receiving at a second chip the flit container and recovering in accordance with a third protocol the one or more flits in the flit container (paras. [0018], [0035], [0050]: recovering flits of a phit at a multi-chip network (i.e. second/third chips) and recovering flits from a phit of a message according to a third protocol).
Regarding claim 19, Prasadh teaches the limitations substantially as follows:
A method of converting flit formatting in a data processing network, comprising:
converting in accordance with a packing logic of a first protocol one or more flits having a first flit format into a flit container having a second flit format different from the first flit format (paras. [0024]-[0025], [0029], [0054], [0069]-[0071]: converting includes packing first flits of a short data format of a first protocol into a phit having a larger data format according to a second protocol);
transmitting at a first chip of the data processing network the flit container having the one or more flits across a link layer of the data processing network in accordance with a second protocol (paras. [0029], [0054], [0069]-[0071]: transmitting flits in a phit across a link layer according to a second protocol); and
receiving at a second chip the flit container transmitted over the link layer and recovering in accordance with a third protocol the one or more flits in the flit container (paras. [0018], [0035], [0050]: recovering flits of a phit at a multi-chip network (i.e. second/third chips) and recovering flits from a phit of a message according to a third protocol).
Prasadh does not explicitly disclose the remaining limitations of claim 19 as follows:
the packing logic of the first protocol preserved in converting the one or more flits having the first flit format into the flit container having the second flit format
However, in the same field of endeavor, Reinig discloses the remaining limitations of claim 19 as follows:
the packing logic of the first protocol preserved in converting the one or more flits having the first flit format into the flit container having the second flit format (paras. [0017]-[0018], [0052], [0056], [0065] [0020], [0022], [0031]: command encoding for first received flits is not changed (i.e. preserved) when the received flits are merged/converted/packed into different flits (i.e. flit container) of a different length (i.e. second flit format), wherein the command encoding is unchanged, no re-encoding is performed, the packets are not inspected and the burst encoding is not modified)
Prasadh and Reinig are combinable because both are from the same field of endeavor of transmitting flits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to integrate Reinig’s method of packing flits with the format of common internal flits into a physical link transport frame without re-encoding or changing the internal bit-offsets and field structures within the common internal flits with the system of Prasadh in order to decrease latency and power requirements.
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Prasadh (US 2017/0171095) and Reinig (US 2016/0173398), as applied to claims 1, 10 and 19, further in view of Willey (US 2014/0115208).
Regarding claims 2 and 12, Prasadh and Reinig teach the limitations of the apparatus of claim 1 and the method of claim 10.
Prasadh teaches the limitations of claims 2 and 12 as follows:
wherein the packer is further configured to pack one or more in the first flit format of the one or more first flits (Prasadh, paras. [0029], [0054], [0069]-[0071]: packing in the first flit data fields, metadata fields, common fields and merged fields)
Prasadh and Reinig do not teach, but in the same field of endeavor, Willey teaches the limitations of claims 2 and 12 as follows:
wherein the packer is further configured to pack one or more message credits and link credits in the first flit format (paras. [0033], [0076], [0080], [0089], [0091]-[0093]: including/packing the number of message class bits/credits and link credits in a flit).
Willey is combinable with Prasadh and Reinig because all are from the same field of endeavor of managing the transmission of flits. The Examiner also notes that Applicant’s Specification admits that “[i]t is noted that SMP protocol requires a link credit for each flit 64B protocol or data flit that is transmitted. It also uses a standalone 64B link credit flit (that does not need a link credit) to send link credits when credits cannot be sent with the protocol flit (may need message credits, or multiple link credits)” (para. [0045]), indicating that inclusion of these credits would have been well known to one of ordinary skill in the art. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to integrate Willey’s method of packing credits for messages and links within the flits with the system of Prasadh and Reinig in order to “improve[] link efficiency and . . simpif[y] logic implementation” (Willey, para. [0097]) and ensure that the physical buffers on the wire don't overflow and that the higher-level protocol logic at the destination can correctly handle the type of message being sent.
Claims 3, 13 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Prasadh (US 2017/0171095) and Reinig (US 2016/0173398), as applied to claims 1, 10 and 19, further in view of Willey (US 20140115208) and Makaram (US 2020/0328879).
Regarding claims 3 and 13, Prasadh, Reinig and Willey teach the limitations of the apparatus of claim 1-2 and the method of claims 10 and 12.
Neither Prasadh, Reinig or Willey teaches the limitations of claims 3 and 13, however in the same field of endeavor, Makaram teaches the limitations of claims 3 and 13 as follows:
wherein the packer is configured to pack one or more link credits and one or more integrity and data encryption (IDE) message authentication codes (MACs), the one or more IDE MACs including a link IDE that is defined for the second protocol (paras. [0066]-[0068]: flit is packed with message authentication codes (MACs) utilized for integrity protection for encryption protocol).
Makaram is combinable with Prasadh, Reinig and Willey because all are from the same field of endeavor of managing the transmission of flits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to integrate Makaram’s method of including MAC codes within the flits with the system of Prasadh, Reinig and Willey in order to increase the security of the system by enabling the MAC codes to be verified to determine the authenticity of the flit.
Regarding claim 21, Prasadh, Reinig and Makaram teach the limitations of the method of claims 1-3.
Makaram teaches the limitations of claim 21 as follows:
The apparatus of claim 3, where the packer inserts IDS message authentication codes in positions defined by the second protocol, without modifying message credit or payload layouts of the first protocol (paras. [0066]-[0068]: A message authentication codes (MACs), utilized for integrity protection for encryption according to AES-GCM/interconnect protocol (i.e. IDS MAC code in positions defined by second protocol) is inserted into the header slot of a flit, which would not modify the message credit tracking of the flit or the payload of the flit).
The same motivation to combine utilized in claim 3 is equally applicable in the instant claim.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Prasadh (US 2017/0171095) and Reinig (US 2016/0173398), as applied to claim 19, further in view of Makaram (US 2020/0328879).
Regarding claim 20, Prasadh and Reinig teach the limitations of the method of claim 19.
Prasadh does not teach the limitations of claim 20, however in the same field of endeavor, Makaram teaches the limitations of claim 20 as follows:
wherein the packer is configured to pack one or more link credits and one or more integrity and data encryption (IDE) message authentication codes (MACs), the one or more IDE MACs including a link IDE that is defined for the second protocol (paras. [0066]-[0068]: flit is packed with message authentication codes (MACs) utilized for integrity protection for encryption protocol).
Makaram is combinable with Prasadh and Reinig because all are from the same field of endeavor of managing the transmission of flits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to integrate Makaram’s method of including MAC codes within the flits with the system of Prasadh and Reinig in order to increase the security of the system by enabling the MAC codes to be verified to determine the authenticity of the flit.
Claims 5-8 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Prasadh (US 2017/0171095) and Reinig (US 2016/0173398), as applied to claims 1 and 10, further in view of Jayasimha (US 2013/0051391).
Regarding claim 5, Prasadh and Reinig teach the limitations of claim 1.
Prasadh and Reinig teach the limitations of claim 5 as follows:
The apparatus of claim 1, the flit converter further comprising:
receive in accordance with the second protocol the flit container packed with one or more packed first flits in a second flit format (Prasadh, paras. [0029], [0054], [0069]-[0071]: receiving according to a second protocol first flits in a phit (i.e. unit of transfer) across a link layer according to a second protocol);
the unpacking logic of the third protocol preserved in unpacking the one or more first flights from the flit container (Reinig, paras. [0017]-[0018], [0052], [0056], [0065] [0020], [0022], [0031]: command encoding for first received flits is not changed (i.e. preserved) when the received flits are merged/converted/packed into different flits (i.e. flit container) of a different length (i.e. second flit format), wherein the command encoding is unchanged, no re-encoding is performed, the packets are not inspected and the burst encoding is not modified)
The same motivation to combine utilized in claim 1 is equally applicable in the instant claim.
Prasadh and Reinig do not explicitly disclose the remaining limitations of claim 5 as follows:
an unpacker configured at a receive stage of the flit converter to:
and unpack in accordance with an unpacking logic of a third protocol the one or more first flits from the flit container.
However, in the same field of endeavor, Jayasimha discloses the remaining limitations of claim 5 as follows:
an unpacker configured at a receive stage of the flit converter to (paras. [0038], [0039], [0078], Figs. 1C & 2: link conversion module packs or unpacks flits received):
and unpack in accordance with an unpacking logic of a third protocol the one or more first flits from the flit container (paras. [0038]-[0040], [0055]-[0056], [0078], Figs. 1C & 2: unpacking according to a third protocol flits received according to a first, second or third protocol illustrated in Fig. 1C such as packetization layer protocol 177, routing layer protocol 179 or message link (ML) protocol).
Prasadh, Reinig and Jayasimha are combinable because they are from the same field of endeavor of managing the transmission of flits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to integrate Jayasimha’s method of using an additional protocol to decode the converted flits back into a regular format with the system of Prasadh and Reinig in order to increase the flexibility of the system by ensuring that converted flits are transformed back into a format the recipient can understand (Jayasimha, para. [0056]).
Regarding claim 6, Prasadh, Reinig and Jayasimha teach the limitations of claims 1 and 5.
Jayasimha teaches the limitations of claim 6 as follows:
The apparatus of claim 5, wherein the packer of the flit converter packs and the unpacker of the flit converter unpacks at a common granularity of aligned data per cycle (paras. [0029], [0031], [0058], [0078]: packing and unpacking flits received based on alignment according to a common data format in each cycle).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to integrate Jayasimha’s method of unpacking according to a common granularity with the system of Prasadh and Reinig in order to enable conversion operations to be “done efficiently and relatively simply” by providing “flexible width conversion in [a] packet” (Jayasimha, para. [0031]).
Regarding claim 17, Prasadh and Reinig teach the limitations of claims 10 and 16.
Prasadh teaches the limitations of claim 17 as follows:
The method of claim 16, wherein recovering the one or more flits in the first flit format (Prasadh, paras. [0029], [0054], [0069]-[0071]: receiving according to a second protocol first flits in a first flit format in a phit (i.e. unit of transfer) across a link layer according to a second protocol)
the unpacking logic of the third protocol preserved in unpacking the one or more first flights from the flit container (Reinig, paras. [0017]-[0018], [0052], [0056], [0065] [0020], [0022], [0031]: command encoding for first received flits is not changed (i.e. preserved) when the received flits are merged/converted/packed into different flits (i.e. flit container) of a different length (i.e. second flit format), wherein the command encoding is unchanged, no re-encoding is performed, the packets are not inspected and the burst encoding is not modified)
The same motivation to combine utilized in claim 1 is equally applicable in the instant claim.
Prasadh and Reinig do not explicitly disclose the remaining limitations of claim 17 as follows:
includes unpacking in accordance with an unpacking logic of the third protocol the one or more flits from the flit container.
However in the same field of endeavor, Jayasimha discloses the remaining limitations of claim 17 as follows:
includes unpacking in accordance with an unpacking logic of the third protocol the one or more flits from the flit container (paras. [0038]-[0040], [0078], Figs. 1C & 2: unpacking according to a third protocol flits received according to a first, second or third protocol illustrated in Fig. 1C such as packetization layer protocol 177, routing layer protocol 179 or message link (ML) protocol).
Prasadh, Reinig and Jayasimha are combinable because they are from the same field of endeavor of managing the transmission of flits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to integrate Jayasimha’s method of using an additional protocol to decode the converted flits back into a regular format with the system of Prasadh and Reinig in order to increase the flexibility of the system by ensuring that converted flits are transformed back into a format the recipient can understand (Jayasimha, para. [0056]).
Regarding claims 7 and 18, Prasadh, Reinig and Jayasimha teach the limitations of the apparatus of claims 1 and 5-6 and the method of claims 10 and 16-17.
Prasadh teaches the limitations of claims 7 and 18 as follows:
wherein the flit converter is configured to pack n chunks over n sequential cycles and unpack n chunks over n sequential cycles (Prasadh, paras. [0030], [0051], [0054], [0056], [0062], [0067]: packing over cycles of an SoC clock/processor), where each chunk of the n chunks has an equal number of slots (Prasadh, paras. [0051], [0063]: where each of the chunks has a slot).
Regarding claim 8, Prasadh, Reinig and Jayasimha teach the limitations of claims 1 and 5.
Prasadh teaches the limitations of claim 8 as follows:
The apparatus of claim 5, wherein the packer is configured to pack multiples of the one or more first flits into the flit container and the unpacker is configured to unpack multiples of the one or more first flits from the flit container (paras. [0025], [0035], [0054], [0069]-[0071]: packing multiple flits into a phit and reassembling the packet by reassembling the flits from the phit).
Prior art not relied upon but applied/considered includes:
1) Safranek (US 11880686 B2) teaches a computing device 100 includes a conversion circuit 132 for converting between a first communication format employed on the system bus 112 and a protocol employed by the link interface circuit 128 in response to memory instructions received on the system bus 112. The conversion circuit 132 performs a conversion in the reverse direction when responses bound for the computing device 100 are received from external devices. In some examples, the computing device 100 may employ compute express link (CXL) protocols to maintain data coherence with external devices. In such examples, the conversion circuit 132 generates FLITs according to the CXL protocols in response to receiving memory instructions on the system bus 112. (col. 4, ll. 40-55).
Conclusion
For the above reasons, claims 1-8 and 10-21 are rejected.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHARON S LYNCH whose telephone number is (571)272-4583. The examiner can normally be reached on 10AM-6PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taghi T Arani can be reached on 571-272-3787. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHARON S LYNCH/Primary Examiner, Art Unit 2438
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